Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml

Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml

File Facts

System
Linux kernel
Corpus path
Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml
Extension
.yaml
Size
3294 bytes
Lines
113
Domain
Support Tooling And Documentation
Bucket
Documentation
Inferred role
Support Tooling And Documentation: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

Dependency Surface

Detected Declarations

Annotated Snippet

# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/qcom,pdc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: PDC interrupt controller

maintainers:
  - Bjorn Andersson <bjorn.andersson@linaro.org>

description: |
  Qualcomm Technologies Inc. SoCs based on the RPM Hardened architecture have a
  Power Domain Controller (PDC) that is on always-on domain. In addition to
  providing power control for the power domains, the hardware also has an
  interrupt controller that can be used to help detect edge low interrupts as
  well detect interrupts when the GIC is non-operational.

  GIC is parent interrupt controller at the highest level. Platform interrupt
  controller PDC is next in hierarchy, followed by others. Drivers requiring
  wakeup capabilities of their device interrupts routed through the PDC, must
  specify PDC as their interrupt controller and request the PDC port associated
  with the GIC interrupt. See example below.

properties:
  compatible:
    items:
      - enum:
          - qcom,eliza-pdc
          - qcom,glymur-pdc
          - qcom,hawi-pdc
          - qcom,kaanapali-pdc
          - qcom,maili-pdc
          - qcom,milos-pdc
          - qcom,nord-pdc
          - qcom,qcs615-pdc
          - qcom,qcs8300-pdc
          - qcom,qdu1000-pdc
          - qcom,sa8255p-pdc
          - qcom,sa8775p-pdc
          - qcom,sar2130p-pdc
          - qcom,sc7180-pdc
          - qcom,sc7280-pdc
          - qcom,sc8180x-pdc
          - qcom,sc8280xp-pdc
          - qcom,sdm670-pdc
          - qcom,sdm845-pdc
          - qcom,sdx55-pdc
          - qcom,sdx65-pdc
          - qcom,sdx75-pdc
          - qcom,sm4450-pdc
          - qcom,sm6350-pdc
          - qcom,sm8150-pdc
          - qcom,sm8250-pdc
          - qcom,sm8350-pdc
          - qcom,sm8450-pdc
          - qcom,sm8550-pdc
          - qcom,sm8650-pdc
          - qcom,sm8750-pdc
          - qcom,x1e80100-pdc
      - const: qcom,pdc

  reg:
    minItems: 1
    items:
      - description: PDC base register region
      - description: Edge or Level config register for SPI interrupts

  '#interrupt-cells':
    const: 2

Annotation

Implementation Notes