Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.yaml
Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.yaml
File Facts
- System
- Linux kernel
- Corpus path
Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.yaml- Extension
.yaml- Size
- 2926 bytes
- Lines
- 108
- Domain
- Support Tooling And Documentation
- Bucket
- Documentation
- Inferred role
- Support Tooling And Documentation: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.
- Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.
Dependency Surface
dt-bindings/clock/r8a7740-clock.hdt-bindings/interrupt-controller/arm-gic.hdt-bindings/interrupt-controller/irq.h
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/renesas,intc-irqpin.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Renesas Interrupt Controller (INTC) for external pins
maintainers:
- Geert Uytterhoeven <geert+renesas@glider.be>
properties:
compatible:
items:
- enum:
- renesas,intc-irqpin-r8a7740 # R-Mobile A1
- renesas,intc-irqpin-r8a7778 # R-Car M1A
- renesas,intc-irqpin-r8a7779 # R-Car H1
- renesas,intc-irqpin-sh73a0 # SH-Mobile AG5
- const: renesas,intc-irqpin
reg:
minItems: 5
items:
- description: Interrupt control register
- description: Interrupt priority register
- description: Interrupt source register
- description: Interrupt mask register
- description: Interrupt mask clear register
- description: Interrupt control register for ICR0 with IRLM0 bit
interrupt-controller: true
'#interrupt-cells':
const: 2
interrupts:
minItems: 1
maxItems: 8
sense-bitfield-width:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [2, 4]
default: 4
description:
Width of a single sense bitfield in the SENSE register, if different from the
default.
control-parent:
type: boolean
description:
Disable and enable interrupts on the parent interrupt controller, needed for some
broken implementations.
clocks:
maxItems: 1
power-domains:
maxItems: 1
required:
- compatible
- reg
- interrupt-controller
- '#interrupt-cells'
- interrupts
if:
properties:
compatible:
Annotation
- Immediate include surface: `dt-bindings/clock/r8a7740-clock.h`, `dt-bindings/interrupt-controller/arm-gic.h`, `dt-bindings/interrupt-controller/irq.h`.
- Atlas domain: Support Tooling And Documentation / Documentation.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.