Documentation/devicetree/bindings/interrupt-controller/renesas,rzv2h-icu.yaml
Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/interrupt-controller/renesas,rzv2h-icu.yaml
File Facts
- System
- Linux kernel
- Corpus path
Documentation/devicetree/bindings/interrupt-controller/renesas,rzv2h-icu.yaml- Extension
.yaml- Size
- 10276 bytes
- Lines
- 282
- Domain
- Support Tooling And Documentation
- Bucket
- Documentation
- Inferred role
- Support Tooling And Documentation: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.
- Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.
Dependency Surface
dt-bindings/interrupt-controller/arm-gic.hdt-bindings/clock/renesas-cpg-mssr.h
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/renesas,rzv2h-icu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Renesas RZ/{G3E,V2H(P)} Interrupt Control Unit
maintainers:
- Fabrizio Castro <fabrizio.castro.jz@renesas.com>
- Geert Uytterhoeven <geert+renesas@glider.be>
allOf:
- $ref: /schemas/interrupt-controller.yaml#
description:
The Interrupt Control Unit (ICU) handles external interrupts (NMI, IRQ, and
TINT), error interrupts, DMAC requests, GPT interrupts, and internal
interrupts.
properties:
compatible:
enum:
- renesas,r9a09g047-icu # RZ/G3E
- renesas,r9a09g056-icu # RZ/V2N
- renesas,r9a09g057-icu # RZ/V2H(P)
'#interrupt-cells':
description: The first cell is the SPI number of the NMI or the
PORT_IRQ[0-15] interrupt, as per user manual. The second cell is used to
specify the flag.
const: 2
'#address-cells':
const: 0
interrupt-controller: true
reg:
maxItems: 1
interrupts:
minItems: 58
items:
- description: NMI interrupt
- description: PORT_IRQ0 interrupt
- description: PORT_IRQ1 interrupt
- description: PORT_IRQ2 interrupt
- description: PORT_IRQ3 interrupt
- description: PORT_IRQ4 interrupt
- description: PORT_IRQ5 interrupt
- description: PORT_IRQ6 interrupt
- description: PORT_IRQ7 interrupt
- description: PORT_IRQ8 interrupt
- description: PORT_IRQ9 interrupt
- description: PORT_IRQ10 interrupt
- description: PORT_IRQ11 interrupt
- description: PORT_IRQ12 interrupt
- description: PORT_IRQ13 interrupt
- description: PORT_IRQ14 interrupt
- description: PORT_IRQ15 interrupt
- description: GPIO interrupt, TINT0
- description: GPIO interrupt, TINT1
- description: GPIO interrupt, TINT2
- description: GPIO interrupt, TINT3
- description: GPIO interrupt, TINT4
- description: GPIO interrupt, TINT5
- description: GPIO interrupt, TINT6
- description: GPIO interrupt, TINT7
- description: GPIO interrupt, TINT8
Annotation
- Immediate include surface: `dt-bindings/interrupt-controller/arm-gic.h`, `dt-bindings/clock/renesas-cpg-mssr.h`.
- Atlas domain: Support Tooling And Documentation / Documentation.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.