Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml

Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml

File Facts

System
Linux kernel
Corpus path
Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml
Extension
.yaml
Size
5626 bytes
Lines
182
Domain
Support Tooling And Documentation
Bucket
Documentation
Inferred role
Support Tooling And Documentation: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

Dependency Surface

Detected Declarations

Annotated Snippet

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/riscv,aplic.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: RISC-V Advanced Platform Level Interrupt Controller (APLIC)

maintainers:
  - Anup Patel <anup@brainfault.org>

description:
  The RISC-V advanced interrupt architecture (AIA) defines an advanced
  platform level interrupt controller (APLIC) for handling wired interrupts
  in a RISC-V platform. The RISC-V AIA specification can be found at
  https://github.com/riscv/riscv-aia.

  The RISC-V APLIC is implemented as hierarchical APLIC domains where all
  interrupt sources connect to the root APLIC domain and a parent APLIC
  domain can delegate interrupt sources to it's child APLIC domains. There
  is one device tree node for each APLIC domain.

allOf:
  - $ref: /schemas/interrupt-controller.yaml#

properties:
  compatible:
    items:
      - enum:
          - qemu,aplic
          - spacemit,k3-aplic
      - const: riscv,aplic

  reg:
    maxItems: 1

  interrupt-controller: true

  "#interrupt-cells":
    const: 2

  interrupts-extended:
    minItems: 1
    maxItems: 16384
    description:
      Given APLIC domain directly injects external interrupts to a set of
      RISC-V HARTS (or CPUs). Each node pointed to should be a riscv,cpu-intc
      node, which has a CPU node (i.e. RISC-V HART) as parent.

  msi-parent:
    description:
      Given APLIC domain forwards wired interrupts as MSIs to a AIA incoming
      message signaled interrupt controller (IMSIC). If both "msi-parent" and
      "interrupts-extended" properties are present then it means the APLIC
      domain supports both MSI mode and Direct mode in HW. In this case, the
      APLIC driver has to choose between MSI mode or Direct mode.

  riscv,num-sources:
    $ref: /schemas/types.yaml#/definitions/uint32
    minimum: 1
    maximum: 1023
    description:
      Specifies the number of wired interrupt sources supported by this
      APLIC domain.

  riscv,children:
    $ref: /schemas/types.yaml#/definitions/phandle-array
    minItems: 1
    maxItems: 1024
    items:

Annotation

Implementation Notes