Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml

Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml

File Facts

System
Linux kernel
Corpus path
Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
Extension
.yaml
Size
5884 bytes
Lines
189
Domain
Support Tooling And Documentation
Bucket
Documentation
Inferred role
Support Tooling And Documentation: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

Dependency Surface

Detected Declarations

Annotated Snippet

# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
# Copyright (C) 2020 SiFive, Inc.
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/sifive,plic-1.0.0.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: SiFive Platform-Level Interrupt Controller (PLIC)

description:
  SiFive SoCs and other RISC-V SoCs include an implementation of the
  Platform-Level Interrupt Controller (PLIC) high-level specification in
  the RISC-V Privileged Architecture specification. The PLIC connects all
  external interrupts in the system to all hart contexts in the system, via
  the external interrupt source in each hart.

  A hart context is a privilege mode in a hardware execution thread. For example,
  in an 4 core system with 2-way SMT, you have 8 harts and probably at least two
  privilege modes per hart; machine mode and supervisor mode.

  Each interrupt can be enabled on per-context basis. Any context can claim
  a pending enabled interrupt and then release it once it has been handled.

  Each interrupt has a configurable priority. Higher priority interrupts are
  serviced first.  Each context can specify a priority threshold. Interrupts
  with priority below this threshold will not cause the PLIC to raise its
  interrupt line leading to the context.

  The PLIC supports both edge-triggered and level-triggered interrupts. For
  edge-triggered interrupts, the RISC-V PLIC spec allows two responses to edges
  seen while an interrupt handler is active; the PLIC may either queue them or
  ignore them. In the first case, handlers are oblivious to the trigger type, so
  it is not included in the interrupt specifier. In the second case, software
  needs to know the trigger type, so it can reorder the interrupt flow to avoid
  missing interrupts. This special handling is needed by at least the Renesas
  RZ/Five SoC (AX45MP AndesCore with a NCEPLIC100) and the T-HEAD C900 PLIC.

  While the RISC-V ISA doesn't specify a memory layout for the PLIC, the
  "sifive,plic-1.0.0" device is a concrete implementation of the PLIC that
  contains a specific memory layout, which is documented in chapter 8 of the
  SiFive U5 Coreplex Series Manual <https://static.dev.sifive.com/U54-MC-RVCoreIP.pdf>.

  The thead,c900-plic is different from sifive,plic-1.0.0 in opensbi, the
  T-HEAD PLIC implementation requires setting a delegation bit to allow access
  from S-mode. So add thead,c900-plic to distinguish them.

maintainers:
  - Paul Walmsley  <paul.walmsley@sifive.com>
  - Palmer Dabbelt <palmer@dabbelt.com>

properties:
  compatible:
    oneOf:
      - items:
          - enum:
              - andestech,qilai-plic
              - renesas,r9a07g043-plic
          - const: andestech,nceplic100
      - items:
          - enum:
              - anlogic,dr1v90-plic
              - canaan,k210-plic
              - eswin,eic7700-plic
              - microchip,pic64gx-plic
              - sifive,fu540-c000-plic
              - spacemit,k1-plic
              - starfive,jh7100-plic
              - starfive,jh7110-plic
              - tenstorrent,blackhole-plic
          - const: sifive,plic-1.0.0

Annotation

Implementation Notes