Documentation/devicetree/bindings/interrupt-controller/st,spear300-shirq.yaml
Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/interrupt-controller/st,spear300-shirq.yaml
File Facts
- System
- Linux kernel
- Corpus path
Documentation/devicetree/bindings/interrupt-controller/st,spear300-shirq.yaml- Extension
.yaml- Size
- 1891 bytes
- Lines
- 68
- Domain
- Support Tooling And Documentation
- Bucket
- Documentation
- Inferred role
- Support Tooling And Documentation: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.
- Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/st,spear300-shirq.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: SPEAr3xx Shared IRQ controller
maintainers:
- Viresh Kumar <vireshk@kernel.org>
- Shiraz Hashim <shiraz.linux.kernel@gmail.com>
description: |
SPEAr3xx architecture includes shared/multiplexed irqs for certain set of
devices. The multiplexor provides a single interrupt to parent interrupt
controller (VIC) on behalf of a group of devices.
There can be multiple groups available on SPEAr3xx variants but not exceeding
4. The number of devices in a group can differ, further they may share same
set of status/mask registers spanning across different bit masks. Also in some
cases the group may not have enable or other registers. This makes software
little complex.
A single node in the device tree is used to describe the shared interrupt
multiplexer (one node for all groups). A group in the interrupt controller
shares config/control registers with other groups. For example, a 32-bit
interrupt enable/disable config register can accommodate up to 4 interrupt
groups.
properties:
compatible:
enum:
- st,spear300-shirq
- st,spear310-shirq
- st,spear320-shirq
reg:
maxItems: 1
'#interrupt-cells':
const: 1
interrupt-controller: true
interrupts:
description: Interrupt specifier array for SHIRQ groups
minItems: 1
maxItems: 4
required:
- compatible
- reg
- '#interrupt-cells'
- interrupt-controller
- interrupts
additionalProperties: false
examples:
- |
interrupt-controller@b3000000 {
compatible = "st,spear320-shirq";
reg = <0xb3000000 0x1000>;
interrupts = <28 29 30 1>;
#interrupt-cells = <1>;
interrupt-controller;
};
Annotation
- Atlas domain: Support Tooling And Documentation / Documentation.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.