Documentation/devicetree/bindings/interrupt-controller/ti,sci-intr.yaml

Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/interrupt-controller/ti,sci-intr.yaml

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Linux kernel
Corpus path
Documentation/devicetree/bindings/interrupt-controller/ti,sci-intr.yaml
Extension
.yaml
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4515 bytes
Lines
136
Domain
Support Tooling And Documentation
Bucket
Documentation
Inferred role
Support Tooling And Documentation: configuration, schema, or hardware description
Status
atlas-only

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Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/ti,sci-intr.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Texas Instruments K3 Interrupt Router

maintainers:
  - Lokesh Vutla <lokeshvutla@ti.com>

allOf:
  - $ref: /schemas/arm/keystone/ti,k3-sci-common.yaml#

description: |
  The Interrupt Router (INTR) module provides a mechanism to mux M
  interrupt inputs to N interrupt outputs, where all M inputs are selectable
  to be driven per N output.

                                   Interrupt Router
                               +----------------------+
                               |  Inputs     Outputs  |
          +-------+            | +------+    +-----+  |
          | GPIO  |----------->| | irq0 |    |  0  |  |       Host IRQ
          +-------+            | +------+    +-----+  |      controller
                               |    .           .     |      +-------+
          +-------+            |    .           .     |----->|  IRQ  |
          | INTA  |----------->|    .           .     |      +-------+
          +-------+            |    .        +-----+  |
                               | +------+    |  N  |  |
                               | | irqM |    +-----+  |
                               | +------+             |
                               |                      |
                               +----------------------+

  There is one register per output (MUXCNTL_N) that controls the selection.
  Configuration of these MUXCNTL_N registers is done by a system controller
  (like the Device Memory and Security Controller on K3 AM654 SoC). System
  controller will keep track of the used and unused registers within the Router.
  Driver should request the system controller to get the range of GIC IRQs
  assigned to the requesting hosts. It is the drivers responsibility to keep
  track of Host IRQs.

  Communication between the host processor running an OS and the system
  controller happens through a protocol called TI System Control Interface
  (TISCI protocol).

properties:
  compatible:
    const: ti,sci-intr

  ti,intr-trigger-type:
    $ref: /schemas/types.yaml#/definitions/uint32
    enum: [1, 4]
    description: |
      Should be one of the following.
        1 = If intr supports edge triggered interrupts.
        4 = If intr supports level triggered interrupts.

  reg:
    maxItems: 1

  interrupt-controller: true

  '#interrupt-cells':
    enum: [1, 2]
    description: |
      Number of cells in interrupt specifier. Depends on ti,intr-trigger-type:
      - If ti,intr-trigger-type is present: must be 1
        The 1st cell should contain interrupt router input hw number.

Annotation

Implementation Notes