Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml

Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml

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System
Linux kernel
Corpus path
Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml
Extension
.yaml
Size
3309 bytes
Lines
121
Domain
Support Tooling And Documentation
Bucket
Documentation
Inferred role
Support Tooling And Documentation: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

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Annotated Snippet

# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/iommu/arm,smmu-v3.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: ARM SMMUv3 Architecture Implementation

maintainers:
  - Will Deacon <will@kernel.org>
  - Robin Murphy <Robin.Murphy@arm.com>

description: |+
  The SMMUv3 architecture is a significant departure from previous
  revisions, replacing the MMIO register interface with in-memory command
  and event queues and adding support for the ATS and PRI components of
  the PCIe specification.

properties:
  $nodename:
    pattern: "^iommu@[0-9a-f]*"
  compatible:
    oneOf:
      - const: arm,smmu-v3
      - items:
          - enum:
              - nvidia,tegra264-smmu
          - const: arm,smmu-v3

  reg:
    maxItems: 1

  interrupts:
    minItems: 1
    maxItems: 4

  interrupt-names:
    oneOf:
      - const: combined
        description:
          The combined interrupt is optional, and should only be provided if the
          hardware supports just a single, combined interrupt line.
          If provided, then the combined interrupt will be used in preference to
          any others.
      - minItems: 1
        items:
          enum:
            - eventq      # Event Queue not empty
            - gerror      # Global Error activated
            - cmdq-sync   # CMD_SYNC complete
            - priq        # PRI Queue not empty

  '#iommu-cells':
    const: 1

  dma-coherent:
    description: |
      Present if page table walks made by the SMMU are cache coherent with the
      CPU.

      NOTE: this only applies to the SMMU itself, not masters connected
      upstream of the SMMU.

  msi-parent: true

  nvidia,cmdqv:
    description: |
      A phandle to its pairing CMDQV extension for an implementation on NVIDIA
      Tegra SoC.

Annotation

Implementation Notes