Documentation/devicetree/bindings/iommu/nvidia,tegra264-cmdqv.yaml

Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/iommu/nvidia,tegra264-cmdqv.yaml

File Facts

System
Linux kernel
Corpus path
Documentation/devicetree/bindings/iommu/nvidia,tegra264-cmdqv.yaml
Extension
.yaml
Size
949 bytes
Lines
43
Domain
Support Tooling And Documentation
Bucket
Documentation
Inferred role
Support Tooling And Documentation: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

Dependency Surface

Detected Declarations

Annotated Snippet

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/iommu/nvidia,tegra264-cmdqv.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NVIDIA Tegra264 CMDQV

description:
  The CMDQ-Virtualization hardware block is part of the SMMUv3 implementation
  on Tegra264 SoCs. It assists in virtualizing the command queue for the SMMU.

maintainers:
  - Nicolin Chen <nicolinc@nvidia.com>

properties:
  compatible:
    const: nvidia,tegra264-cmdqv

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

required:
  - compatible
  - reg
  - interrupts

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/interrupt-controller/irq.h>

    cmdqv@5200000 {
            compatible = "nvidia,tegra264-cmdqv";
            reg = <0x5200000 0x830000>;
            interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
    };

Annotation

Implementation Notes