Documentation/devicetree/bindings/iommu/riscv,iommu.yaml

Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/iommu/riscv,iommu.yaml

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System
Linux kernel
Corpus path
Documentation/devicetree/bindings/iommu/riscv,iommu.yaml
Extension
.yaml
Size
5619 bytes
Lines
191
Domain
Support Tooling And Documentation
Bucket
Documentation
Inferred role
Support Tooling And Documentation: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

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Annotated Snippet

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/iommu/riscv,iommu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: RISC-V IOMMU Architecture Implementation

maintainers:
  - Tomasz Jeznach <tjeznach@rivosinc.com>

description: |
  The RISC-V IOMMU provides memory address translation and isolation for
  input and output devices, supporting per-device translation context,
  shared process address spaces including the ATS and PRI components of
  the PCIe specification, two stage address translation and MSI remapping.
  It supports identical translation table format to the RISC-V address
  translation tables with page level access and protection attributes.
  Hardware uses in-memory command and fault reporting queues with wired
  interrupt or MSI notifications.

  Visit https://github.com/riscv-non-isa/riscv-iommu for more details.

  For information on assigning RISC-V IOMMU to its peripheral devices,
  see generic IOMMU bindings.

properties:
  # For PCIe IOMMU hardware compatible property should contain the vendor
  # and device ID according to the PCI Bus Binding specification.
  # Since PCI provides built-in identification methods, compatible is not
  # actually required. For non-PCIe hardware implementations 'riscv,iommu'
  # should be specified along with 'reg' property providing MMIO location.
  compatible:
    oneOf:
      - description: Platform (non-PCIe) IOMMU implementations
        items:
          - enum:
              - qemu,riscv-iommu
              - tenstorrent,riscv-iommu
          - const: riscv,iommu
      - description: PCIe IOMMU implementations
        items:
          - enum:
              - pci1efd,edf1
          - const: riscv,pci-iommu

  reg:
    minItems: 1
    items:
      - description:
          For non-PCI devices, base address and size of the IOMMU memory
          mapped registers interface. For PCI IOMMU hardware
          implementation, an address of the IOMMU, as defined in the PCI
          Bus Binding reference.
      - description:
          Region containing platform specific MMRs for machine-mode
          configuration, such as PMA and PMP registers.

  reg-names:
    minItems: 1
    items:
      - const: base
      - const: machine

  '#iommu-cells':
    const: 1
    description:
      The single cell describes the requester id emitted by a master to the
      IOMMU.

Annotation

Implementation Notes