Documentation/devicetree/bindings/mailbox/arm,mhu.yaml
Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/mailbox/arm,mhu.yaml
File Facts
- System
- Linux kernel
- Corpus path
Documentation/devicetree/bindings/mailbox/arm,mhu.yaml- Extension
.yaml- Size
- 4875 bytes
- Lines
- 169
- Domain
- Support Tooling And Documentation
- Bucket
- Documentation
- Inferred role
- Support Tooling And Documentation: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.
- Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mailbox/arm,mhu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ARM MHU Mailbox Controller
maintainers:
- Jassi Brar <jaswinder.singh@linaro.org>
description: |
The ARM's Message-Handling-Unit (MHU) is a mailbox controller that has 3
independent channels/links to communicate with remote processor(s). MHU links
are hardwired on a platform. A link raises interrupt for any received data.
However, there is no specified way of knowing if the sent data has been read
by the remote. This driver assumes the sender polls STAT register and the
remote clears it after having read the data. The last channel is specified to
be a 'Secure' resource, hence can't be used by Linux running NS.
The MHU hardware also allows operations in doorbell mode. The MHU drives the
interrupt signal using a 32-bit register, with all 32-bits logically ORed
together. It provides a set of registers to enable software to set, clear and
check the status of each of the bits of this register independently. The use
of 32 bits per interrupt line enables software to provide more information
about the source of the interrupt. For example, each bit of the register can
be associated with a type of event that can contribute to raising the
interrupt. Each of the 32-bits can be used as "doorbell" to alert the remote
processor.
# We need a select here so we don't match all nodes with 'arm,primecell'
select:
properties:
compatible:
contains:
enum:
- arm,mhu
- arm,mhu-doorbell
required:
- compatible
properties:
compatible:
oneOf:
- description: Data transfer mode
items:
- const: arm,mhu
- const: arm,primecell
- description: Doorbell mode
items:
- const: arm,mhu-doorbell
- const: arm,primecell
reg:
maxItems: 1
interrupts:
minItems: 2
items:
- description: low-priority non-secure
- description: high-priority non-secure
- description: Secure
clocks:
maxItems: 1
clock-names:
items:
- const: apb_pclk
Annotation
- Atlas domain: Support Tooling And Documentation / Documentation.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.