Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml
Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml
File Facts
- System
- Linux kernel
- Corpus path
Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml- Extension
.yaml- Size
- 4461 bytes
- Lines
- 138
- Domain
- Support Tooling And Documentation
- Bucket
- Documentation
- Inferred role
- Support Tooling And Documentation: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.
- Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
dt-bindings/interrupt-controller/arm-gic.hdt-bindings/mailbox/tegra186-hsp.h
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mailbox/nvidia,tegra186-hsp.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA Tegra Hardware Synchronization Primitives (HSP)
maintainers:
- Thierry Reding <thierry.reding@gmail.com>
- Jon Hunter <jonathanh@nvidia.com>
description: |
The HSP modules are used for the processors to share resources and
communicate together. It provides a set of hardware synchronization
primitives for interprocessor communication. So the interprocessor
communication (IPC) protocols can use hardware synchronization
primitives, when operating between two processors not in an SMP
relationship.
The features that HSP supported are shared mailboxes, shared
semaphores, arbitrated semaphores and doorbells.
The mbox specifier of the "mboxes" property in the client node should
contain two cells. The first cell determines the HSP type and the
second cell is used to identify the mailbox that the client is going
to use.
For shared mailboxes, the first cell composed of two fields:
- bits 15..8:
A bit mask of flags that further specifies the type of shared
mailbox to be used (based on the data size). If no flag is
specified then, 32-bit shared mailbox is used.
- bits 7..0:
Defines the type of the mailbox to be used. This field should be
TEGRA_HSP_MBOX_TYPE_SM for shared mailboxes.
For doorbells, the second cell specifies the index of the doorbell to
use.
For shared mailboxes, the second cell is composed of two fields:
- bits 31..24:
A bit mask of flags that further specify how the shared mailbox
will be used. Valid flags are:
- bit 31:
Defines the direction of the mailbox. If set, the mailbox
will be used as a producer (i.e. used to send data). If
cleared, the mailbox is the consumer of data sent by a
producer.
- bits 23..0:
The index of the shared mailbox to use. The number of available
mailboxes may vary by instance of the HSP block and SoC
generation.
The following file contains definitions that can be used to
construct mailbox specifiers:
<dt-bindings/mailbox/tegra186-hsp.h>
properties:
compatible:
oneOf:
- enum:
- nvidia,tegra186-hsp
- nvidia,tegra194-hsp
- nvidia,tegra264-hsp
- items:
- const: nvidia,tegra234-hsp
- const: nvidia,tegra194-hsp
Annotation
- Immediate include surface: `dt-bindings/interrupt-controller/arm-gic.h`, `dt-bindings/mailbox/tegra186-hsp.h`.
- Atlas domain: Support Tooling And Documentation / Documentation.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.