Documentation/devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml
Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml
File Facts
- System
- Linux kernel
- Corpus path
Documentation/devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml- Extension
.yaml- Size
- 1305 bytes
- Lines
- 57
- Domain
- Support Tooling And Documentation
- Bucket
- Documentation
- Inferred role
- Support Tooling And Documentation: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.
- Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.
Dependency Surface
dt-bindings/interrupt-controller/arm-gic.h
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/mailbox/qcom,cpucp-mbox.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Technologies, Inc. CPUCP Mailbox Controller
maintainers:
- Sibi Sankar <quic_sibis@quicinc.com>
description:
The CPUSS Control Processor (CPUCP) mailbox controller enables communication
between AP and CPUCP by acting as a doorbell between them.
properties:
compatible:
oneOf:
- items:
- enum:
- qcom,glymur-cpucp-mbox
- qcom,kaanapali-cpucp-mbox
- qcom,sm8750-cpucp-mbox
- const: qcom,x1e80100-cpucp-mbox
- enum:
- qcom,x1e80100-cpucp-mbox
reg:
items:
- description: CPUCP rx register region
- description: CPUCP tx register region
interrupts:
maxItems: 1
"#mbox-cells":
const: 1
required:
- compatible
- reg
- interrupts
- "#mbox-cells"
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
mailbox@17430000 {
compatible = "qcom,x1e80100-cpucp-mbox";
reg = <0x17430000 0x10000>, <0x18830000 0x10000>;
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
#mbox-cells = <1>;
};
Annotation
- Immediate include surface: `dt-bindings/interrupt-controller/arm-gic.h`.
- Atlas domain: Support Tooling And Documentation / Documentation.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.