Documentation/devicetree/bindings/media/cdns,csi2rx.yaml

Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/media/cdns,csi2rx.yaml

File Facts

System: Linux kernel
Corpus path: Documentation/devicetree/bindings/media/cdns,csi2rx.yaml
Extension: .yaml
Size: 5244 bytes
Lines: 211
Domain: Support Tooling And Documentation
Bucket: Documentation
Inferred role: Support Tooling And Documentation: configuration, schema, or hardware description
Status: atlas-only

Why This File Exists

Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

Dependency Surface

No C-style include directives detected by the generator.

Detected Declarations

No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/cdns,csi2rx.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Cadence MIPI-CSI2 RX controller

maintainers:
  - Maxime Ripard <mripard@kernel.org>

description:
  The Cadence MIPI-CSI2 RX controller is a CSI-2 bridge supporting up to 4 CSI
  lanes in input, and 4 different pixel streams in output.

properties:
  compatible:
    items:
      - enum:
          - starfive,jh7110-csi2rx
          - ti,j721e-csi2rx
      - const: cdns,csi2rx

  reg:
    maxItems: 1

  interrupts:
    maxItems: 2

  interrupt-names:
    items:
      - const: error_irq
      - const: irq

  clocks:
    items:
      - description: CSI2Rx system clock
      - description: Gated Register bank clock for APB interface
      - description: pixel Clock for Stream interface 0
      - description: pixel Clock for Stream interface 1
      - description: pixel Clock for Stream interface 2
      - description: pixel Clock for Stream interface 3

  clock-names:
    items:
      - const: sys_clk
      - const: p_clk
      - const: pixel_if0_clk
      - const: pixel_if1_clk
      - const: pixel_if2_clk
      - const: pixel_if3_clk

  resets:
    items:
      - description: CSI2Rx system reset
      - description: Gated Register bank reset for APB interface
      - description: pixel reset for Stream interface 0
      - description: pixel reset for Stream interface 1
      - description: pixel reset for Stream interface 2
      - description: pixel reset for Stream interface 3

  reset-names:
    items:
      - const: sys
      - const: reg_bank
      - const: pixel_if0
      - const: pixel_if1
      - const: pixel_if2
      - const: pixel_if3

Annotation

Atlas domain: Support Tooling And Documentation / Documentation.
Implementation status: atlas-only.

Implementation Notes

This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.