Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml

Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml

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Linux kernel
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Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml
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.yaml
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9662 bytes
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Support Tooling And Documentation
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Documentation
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Support Tooling And Documentation: configuration, schema, or hardware description
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atlas-only

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Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/mediatek,vcodec-subdev-decoder.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: MediaTek Video Decode Accelerator With Multi Hardware

maintainers:
  - Yunfei Dong <yunfei.dong@mediatek.com>

description: |
  MediaTek Video Decode Accelerator is the video decoding hardware present in
  MediaTek SoCs that supports high-resolution decoding functionalities.
  It consists of parent and child nodes.

  The decoder hardware block diagram is shown below:

    +------------------------------------------------+------------------------------+
    |                                                |                              |
    |  input -> LAT-SoC HW -> LAT HW -> LAT buffer --|--> Core HW -> output buffer  |
    |              ||           ||                   |       ||                     |
    +--------------||-----------||-------------------+-------||---------------------+
                    LAT Workqueue                    |  Core Workqueue       <parent>
    ---------------||-----------||-------------------|-------||----------------------
                   ||<----------||---------HW index--------->||              <child>
                   \/           \/                           \/
           +-------------------------------------------------------------+
           |                          enable/disable                     |
           |                 clk     power    irq    iommu               |
           |                   (lat/lat-soc/core0/core1)                 |
           +-------------------------------------------------------------+

  The child nodes represent the individual hardware blocks within the decoding
  pipeline, such as LAT-SoC, LAT and Core.
  Each child node is responsible for managing the dedicated resources of the
  hardware, such as clocks, power domains, interrupts and IOMMUs.

  The parent node is a central point of control for the child nodes.
  It identifies the specific video decoding pipeline architecture used by the
  SoC, manages the shared resources like workqueues and platform data, and
  handles V4L2 API calls on behalf of the underlying hardware.

  The parent utilizes two workqueues to manage the decoding process.
  1. LAT Workqueue, for LAT-SoC and LAT decoder:
     Its workers take input bitstream and LAT buffer, enable the hardware for
     decoding tasks, write the result to LAT buffer, and disable the hardware
     after the LAT decoding is done.
  2. Core Workqueue, for Core decoder:
     Its workers take LAT buffer and output buffer, enable the hardware for
     decoding tasks, write the result to output buffer, and disable the hardware
     after the Core decoding is done.

  These hardware decode each frame cyclically.

  The hardware might be associated with different SMI-common devices.
  To prevent IOMMU faults during DRAM access in such cases, each hardware with
  the unique SMI-common device must be placed under a separate parent node in
  the device tree.

  LAT-SoC refers to another hardware block that connected to additional LARB
  (local arbiter) ports, such as RDMA and UFO.
  It requires independent power and clock control to work with LAT decoder, and
  it doesn't have a dedicated interrupt.

  The used video decoding pipeline architecture across various Mediatek SoC:
    MT8195: LAT-SoC + LAT + Core
    MT8192: LAT + Core
    MT8188: LAT + Core
    MT8186: Core

Annotation

Implementation Notes