Documentation/devicetree/bindings/media/nxp,imx8-jpeg.yaml
Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/media/nxp,imx8-jpeg.yaml
File Facts
- System
- Linux kernel
- Corpus path
Documentation/devicetree/bindings/media/nxp,imx8-jpeg.yaml- Extension
.yaml- Size
- 3930 bytes
- Lines
- 128
- Domain
- Support Tooling And Documentation
- Bucket
- Documentation
- Inferred role
- Support Tooling And Documentation: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.
- Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.
Dependency Surface
dt-bindings/clock/imx8-lpcg.hdt-bindings/interrupt-controller/arm-gic.hdt-bindings/firmware/imx/rsrc.h
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/nxp,imx8-jpeg.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: i.MX8QXP/QM JPEG decoder/encoder
maintainers:
- Mirela Rabulea <mirela.rabulea@nxp.com>
description: |-
The JPEG decoder/encoder present in iMX8QXP and iMX8QM SoCs is an
ISO/IEC 10918-1 JPEG standard compliant decoder/encoder, for Baseline
and Extended Sequential DCT modes.
properties:
compatible:
oneOf:
- items:
enum:
- nxp,imx8qxp-jpgdec
- nxp,imx8qxp-jpgenc
- items:
- enum:
- nxp,imx8qm-jpgdec
- nxp,imx95-jpgdec
- const: nxp,imx8qxp-jpgdec
- items:
- enum:
- nxp,imx8qm-jpgenc
- nxp,imx95-jpgenc
- const: nxp,imx8qxp-jpgenc
reg:
maxItems: 1
clocks:
items:
- description: AXI DMA engine clock for fetching JPEG bitstream from memory (per)
- description: IP bus clock for register access (ipg)
interrupts:
description: |
There are 4 slots available in the IP, which the driver may use
If a certain slot is used, it should have an associated interrupt
The interrupt with index i is assumed to be for slot i
minItems: 1 # At least one slot is needed by the driver
maxItems: 4 # The IP has 4 slots available for use
power-domains:
description:
List of phandle and PM domain specifier as documented in
Documentation/devicetree/bindings/power/power_domain.txt
minItems: 1 # Wrapper and all slots
maxItems: 5 # Wrapper and 4 slots
sram:
maxItems: 1
description:
The SRAM can be used for descriptor storage, which may improve bus
utilization.
required:
- compatible
- reg
- clocks
- interrupts
- power-domains
Annotation
- Immediate include surface: `dt-bindings/clock/imx8-lpcg.h`, `dt-bindings/interrupt-controller/arm-gic.h`, `dt-bindings/firmware/imx/rsrc.h`.
- Atlas domain: Support Tooling And Documentation / Documentation.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.