Documentation/devicetree/bindings/memory-controllers/intel,ixp4xx-expansion-bus-controller.yaml

Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/memory-controllers/intel,ixp4xx-expansion-bus-controller.yaml

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System
Linux kernel
Corpus path
Documentation/devicetree/bindings/memory-controllers/intel,ixp4xx-expansion-bus-controller.yaml
Extension
.yaml
Size
3323 bytes
Lines
108
Domain
Support Tooling And Documentation
Bucket
Documentation
Inferred role
Support Tooling And Documentation: configuration, schema, or hardware description
Status
atlas-only

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Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

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Annotated Snippet

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/intel,ixp4xx-expansion-bus-controller.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Intel IXP4xx Expansion Bus Controller

description: |
  The IXP4xx expansion bus controller handles access to devices on the
  memory-mapped expansion bus on the Intel IXP4xx family of system on chips,
  including IXP42x, IXP43x, IXP45x and IXP46x.

maintainers:
  - Linus Walleij <linusw@kernel.org>

properties:
  $nodename:
    pattern: '^bus@[0-9a-f]+$'

  compatible:
    items:
      - enum:
          - intel,ixp42x-expansion-bus-controller
          - intel,ixp43x-expansion-bus-controller
          - intel,ixp45x-expansion-bus-controller
          - intel,ixp46x-expansion-bus-controller
      - const: syscon

  reg:
    description: Control registers for the expansion bus, these are not
      inside the memory range handled by the expansion bus.
    maxItems: 1

  native-endian:
    $ref: /schemas/types.yaml#/definitions/flag
    description: The IXP4xx has a peculiar MMIO access scheme, as it changes
      the access pattern for words (swizzling) on the bus depending on whether
      the SoC is running in big-endian or little-endian mode. Thus the
      registers must always be accessed using native endianness.

  "#address-cells":
    description: |
      The first cell is the chip select number.
      The second cell is the address offset within the bank.
    const: 2

  "#size-cells":
    const: 1

  ranges: true
  dma-ranges: true

patternProperties:
  "^.*@[0-7],[0-9a-f]+$":
    description: Devices attached to chip selects are represented as
      subnodes.
    type: object
    $ref: /schemas/memory-controllers/intel,ixp4xx-expansion-peripheral-props.yaml#
    additionalProperties: true

required:
  - compatible
  - reg
  - native-endian
  - "#address-cells"
  - "#size-cells"
  - ranges
  - dma-ranges

Annotation

Implementation Notes