Documentation/devicetree/bindings/memory-controllers/mvebu-devbus.txt
Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/memory-controllers/mvebu-devbus.txt
File Facts
- System
- Linux kernel
- Corpus path
Documentation/devicetree/bindings/memory-controllers/mvebu-devbus.txt- Extension
.txt- Size
- 7094 bytes
- Lines
- 178
- Domain
- Support Tooling And Documentation
- Bucket
- Documentation
- Inferred role
- Support Tooling And Documentation: documentation
- Status
- atlas-only
Why This File Exists
Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.
- Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
Device tree bindings for MVEBU Device Bus controllers
The Device Bus controller available in some Marvell's SoC allows to control
different types of standard memory and I/O devices such as NOR, NAND, and FPGA.
The actual devices are instantiated from the child nodes of a Device Bus node.
Required properties:
- compatible: Armada 370/XP SoC are supported using the
"marvell,mvebu-devbus" compatible string.
Orion5x SoC are supported using the
"marvell,orion-devbus" compatible string.
- reg: A resource specifier for the register space.
This is the base address of a chip select within
the controller's register space.
(see the example below)
- #address-cells: Must be set to 1
- #size-cells: Must be set to 1
- ranges: Must be set up to reflect the memory layout with four
integer values for each chip-select line in use:
0 <physical address of mapping> <size>
Optional properties:
- devbus,keep-config This property can optionally be used to keep
using the timing parameters set by the
bootloader. It makes all the timing properties
described below unused.
Timing properties for child nodes:
Read parameters:
- devbus,turn-off-ps: Defines the time during which the controller does not
drive the AD bus after the completion of a device read.
This prevents contentions on the Device Bus after a read
cycle from a slow device.
Mandatory, except if devbus,keep-config is used.
- devbus,bus-width: Defines the bus width, in bits (e.g. <16>).
Mandatory, except if devbus,keep-config is used.
- devbus,badr-skew-ps: Defines the time delay from from A[2:0] toggle,
to read data sample. This parameter is useful for
synchronous pipelined devices, where the address
precedes the read data by one or two cycles.
Mandatory, except if devbus,keep-config is used.
- devbus,acc-first-ps: Defines the time delay from the negation of
ALE[0] to the cycle that the first read data is sampled
by the controller.
Mandatory, except if devbus,keep-config is used.
- devbus,acc-next-ps: Defines the time delay between the cycle that
samples data N and the cycle that samples data N+1
(in burst accesses).
Mandatory, except if devbus,keep-config is used.
- devbus,rd-setup-ps: Defines the time delay between DEV_CSn assertion to
DEV_OEn assertion. If set to 0 (default),
DEV_OEn and DEV_CSn are asserted at the same cycle.
This parameter has no affect on <acc-first-ps> parameter
(no affect on first data sample). Set <rd-setup-ps>
to a value smaller than <acc-first-ps>.
Mandatory for "marvell,mvebu-devbus" compatible string,
except if devbus,keep-config is used.
Annotation
- Atlas domain: Support Tooling And Documentation / Documentation.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.