Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-mc.yaml

Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-mc.yaml

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System
Linux kernel
Corpus path
Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-mc.yaml
Extension
.yaml
Size
1865 bytes
Lines
80
Domain
Support Tooling And Documentation
Bucket
Documentation
Inferred role
Support Tooling And Documentation: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

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Annotated Snippet

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra20-mc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NVIDIA Tegra20 SoC Memory Controller

maintainers:
  - Dmitry Osipenko <digetx@gmail.com>
  - Jon Hunter <jonathanh@nvidia.com>
  - Thierry Reding <thierry.reding@gmail.com>

description: |
  The Tegra20 Memory Controller merges request streams from various client
  interfaces into request stream(s) for the various memory target devices,
  and returns response data to the various clients. The Memory Controller
  has a configurable arbitration algorithm to allow the user to fine-tune
  performance among the various clients.

  Tegra20 Memory Controller includes the GART (Graphics Address Relocation
  Table) which allows Memory Controller to provide a linear view of a
  fragmented memory pages.

properties:
  compatible:
    const: nvidia,tegra20-mc-gart

  reg:
    items:
      - description: controller registers
      - description: GART registers

  clocks:
    maxItems: 1

  clock-names:
    items:
      - const: mc

  interrupts:
    maxItems: 1

  "#reset-cells":
    const: 1

  "#iommu-cells":
    const: 0

  "#interconnect-cells":
    const: 1

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names
  - "#reset-cells"
  - "#iommu-cells"
  - "#interconnect-cells"

additionalProperties: false

examples:
  - |
    memory-controller@7000f000 {
        compatible = "nvidia,tegra20-mc-gart";
        reg = <0x7000f000 0x400>, /* Controller registers */
              <0x58000000 0x02000000>; /* GART aperture */

Annotation

Implementation Notes