Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-emc.yaml

Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-emc.yaml

File Facts

System
Linux kernel
Corpus path
Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-emc.yaml
Extension
.yaml
Size
13450 bytes
Lines
356
Domain
Support Tooling And Documentation
Bucket
Documentation
Inferred role
Support Tooling And Documentation: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

Dependency Surface

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Annotated Snippet

# SPDX-License-Identifier: (GPL-2.0)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra30-emc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NVIDIA Tegra30 SoC External Memory Controller

maintainers:
  - Dmitry Osipenko <digetx@gmail.com>
  - Jon Hunter <jonathanh@nvidia.com>
  - Thierry Reding <thierry.reding@gmail.com>

description: |
  The EMC interfaces with the off-chip SDRAM to service the request stream
  sent from Memory Controller. The EMC also has various performance-affecting
  settings beyond the obvious SDRAM configuration parameters and initialization
  settings. Tegra30 EMC supports multiple JEDEC standard protocols: LPDDR2,
  LPDDR3, and DDR3.

properties:
  compatible:
    const: nvidia,tegra30-emc

  reg:
    maxItems: 1

  clocks:
    maxItems: 1

  interrupts:
    maxItems: 1

  "#interconnect-cells":
    const: 0

  nvidia,memory-controller:
    $ref: /schemas/types.yaml#/definitions/phandle
    description:
      Phandle of the Memory Controller node.

  power-domains:
    maxItems: 1
    description:
      Phandle of the SoC "core" power domain.

  operating-points-v2:
    description:
      Should contain freqs and voltages and opp-supported-hw property, which
      is a bitfield indicating SoC speedo ID mask.

patternProperties:
  "^emc-timings-[0-9]+$":
    type: object
    properties:
      nvidia,ram-code:
        $ref: /schemas/types.yaml#/definitions/uint32
        description:
          Value of RAM_CODE this timing set is used for.

    patternProperties:
      "^timing-[0-9]+$":
        type: object
        properties:
          clock-frequency:
            description:
              Memory clock rate in Hz.
            minimum: 1000000
            maximum: 900000000

Annotation

Implementation Notes