Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-mc.yaml

Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-mc.yaml

File Facts

System
Linux kernel
Corpus path
Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-mc.yaml
Extension
.yaml
Size
5429 bytes
Lines
173
Domain
Support Tooling And Documentation
Bucket
Documentation
Inferred role
Support Tooling And Documentation: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

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Detected Declarations

Annotated Snippet

# SPDX-License-Identifier: (GPL-2.0)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra30-mc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NVIDIA Tegra30 SoC Memory Controller

maintainers:
  - Dmitry Osipenko <digetx@gmail.com>
  - Jon Hunter <jonathanh@nvidia.com>
  - Thierry Reding <thierry.reding@gmail.com>

description: |
  Tegra30 Memory Controller architecturally consists of the following parts:

    Arbitration Domains, which can handle a single request or response per
    clock from a group of clients. Typically, a system has a single Arbitration
    Domain, but an implementation may divide the client space into multiple
    Arbitration Domains to increase the effective system bandwidth.

    Protocol Arbiter, which manage a related pool of memory devices. A system
    may have a single Protocol Arbiter or multiple Protocol Arbiters.

    Memory Crossbar, which routes request and responses between Arbitration
    Domains and Protocol Arbiters. In the simplest version of the system, the
    Memory Crossbar is just a pass through between a single Arbitration Domain
    and a single Protocol Arbiter.

    Global Resources, which include things like configuration registers which
    are shared across the Memory Subsystem.

  The Tegra30 Memory Controller handles memory requests from internal clients
  and arbitrates among them to allocate memory bandwidth for DDR3L and LPDDR2
  SDRAMs.

properties:
  compatible:
    const: nvidia,tegra30-mc

  reg:
    maxItems: 1

  clocks:
    maxItems: 1

  clock-names:
    items:
      - const: mc

  interrupts:
    maxItems: 1

  "#reset-cells":
    const: 1

  "#iommu-cells":
    const: 1

  "#interconnect-cells":
    const: 1

patternProperties:
  "^emc-timings-[0-9]+$":
    type: object
    properties:
      nvidia,ram-code:
        $ref: /schemas/types.yaml#/definitions/uint32
        description:
          Value of RAM_CODE this timing set is used for.

Annotation

Implementation Notes