Documentation/devicetree/bindings/memory-controllers/samsung,exynos4210-srom-peripheral-props.yaml
Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/memory-controllers/samsung,exynos4210-srom-peripheral-props.yaml
File Facts
- System
- Linux kernel
- Corpus path
Documentation/devicetree/bindings/memory-controllers/samsung,exynos4210-srom-peripheral-props.yaml- Extension
.yaml- Size
- 1205 bytes
- Lines
- 36
- Domain
- Support Tooling And Documentation
- Bucket
- Documentation
- Inferred role
- Support Tooling And Documentation: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.
- Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/samsung,exynos4210-srom-peripheral-props.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Peripheral Properties for Samsung Exynos SoC SROM Controller
maintainers:
- Krzysztof Kozlowski <krzk@kernel.org>
properties:
samsung,srom-page-mode:
description:
If page mode is set, 4 data page mode will be configured,
else normal (1 data) page mode will be set.
type: boolean
samsung,srom-timing:
$ref: /schemas/types.yaml#/definitions/uint32-array
minItems: 6
maxItems: 6
description: |
Array of 6 integers, specifying bank timings in the following order:
Tacp, Tcah, Tcoh, Tacc, Tcos, Tacs.
Each value is specified in cycles and has the following meaning
and valid range:
Tacp: Page mode access cycle at Page mode (0 - 15)
Tcah: Address holding time after CSn (0 - 15)
Tcoh: Chip selection hold on OEn (0 - 15)
Tacc: Access cycle (0 - 31, the actual time is N + 1)
Tcos: Chip selection set-up before OEn (0 - 15)
Tacs: Address set-up before CSn (0 - 15)
additionalProperties: true
Annotation
- Atlas domain: Support Tooling And Documentation / Documentation.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.