Documentation/devicetree/bindings/memory-controllers/samsung,exynos5422-dmc.yaml

Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/memory-controllers/samsung,exynos5422-dmc.yaml

File Facts

System
Linux kernel
Corpus path
Documentation/devicetree/bindings/memory-controllers/samsung,exynos5422-dmc.yaml
Extension
.yaml
Size
4242 bytes
Lines
140
Domain
Support Tooling And Documentation
Bucket
Documentation
Inferred role
Support Tooling And Documentation: configuration, schema, or hardware description
Status
atlas-only

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Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

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Annotated Snippet

# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/samsung,exynos5422-dmc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: |
  Samsung Exynos5422 SoC frequency and voltage scaling for Dynamic Memory
  Controller device

maintainers:
  - Krzysztof Kozlowski <krzk@kernel.org>
  - Lukasz Luba <lukasz.luba@arm.com>

description: |
  The Samsung Exynos5422 SoC has DMC (Dynamic Memory Controller) to which the
  DRAM memory chips are connected. The driver is to monitor the controller in
  runtime and switch frequency and voltage. To monitor the usage of the
  controller in runtime, the driver uses the PPMU (Platform Performance
  Monitoring Unit), which is able to measure the current load of the memory.
  When 'userspace' governor is used for the driver, an application is able to
  switch the DMC and memory frequency.

properties:
  compatible:
    items:
      - const: samsung,exynos5422-dmc

  clock-names:
    items:
      - const: fout_spll
      - const: mout_sclk_spll
      - const: ff_dout_spll2
      - const: fout_bpll
      - const: mout_bpll
      - const: sclk_bpll
      - const: mout_mx_mspll_ccore
      - const: mout_mclk_cdrex

  clocks:
    minItems: 8
    maxItems: 8

  devfreq-events:
    $ref: /schemas/types.yaml#/definitions/phandle-array
    minItems: 1
    maxItems: 16
    items:
      maxItems: 1
    description: phandles of the PPMU events used by the controller.

  device-handle:
    $ref: /schemas/types.yaml#/definitions/phandle
    description: |
      phandle of the connected DRAM memory device. For more information please
      refer to jedec,lpddr3.yaml.

  operating-points-v2: true

  interrupts:
    items:
      - description: DMC internal performance event counters in DREX0
      - description: DMC internal performance event counters in DREX1

  interrupt-names:
    items:
      - const: drex_0
      - const: drex_1

  reg:

Annotation

Implementation Notes