Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml

Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml

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System
Linux kernel
Corpus path
Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml
Extension
.yaml
Size
7658 bytes
Lines
299
Domain
Support Tooling And Documentation
Bucket
Documentation
Inferred role
Support Tooling And Documentation: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

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Annotated Snippet

# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/mfd/aspeed,ast2x00-scu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Aspeed System Control Unit

description:
  The Aspeed System Control Unit manages the global behaviour of the SoC,
  configuring elements such as clocks, pinmux, and reset.
  In AST2700 SOC which has two soc connection, each soc have its own scu
  register control, ast2700-scu0 for soc0, ast2700-scu1 for soc1.

maintainers:
  - Joel Stanley <joel@jms.id.au>
  - Andrew Jeffery <andrew@aj.id.au>

properties:
  compatible:
    items:
      - enum:
          - aspeed,ast2400-scu
          - aspeed,ast2500-scu
          - aspeed,ast2600-scu
          - aspeed,ast2700-scu0
          - aspeed,ast2700-scu1
      - const: syscon
      - const: simple-mfd

  reg:
    maxItems: 1

  ranges: true

  '#address-cells':
    minimum: 1
    maximum: 2

  '#size-cells':
    const: 1

  '#clock-cells':
    const: 1

  '#reset-cells':
    const: 1

  memory-region:
    items:
      - description: Region mapped through the first SSP address window.
      - description: Region mapped through the second SSP address window.
      - description: Region mapped through the TSP address window.

  memory-region-names:
    items:
      - const: ssp-0
      - const: ssp-1
      - const: tsp

patternProperties:
  '^p2a-control@[0-9a-f]+$':
    description: >
      PCI-to-AHB Bridge Control

      The bridge is available on platforms with the VGA enabled on the Aspeed
      device. In this case, the host has access to a 64KiB window into all of
      the BMC's memory. The BMC can disable this bridge. If the bridge is
      enabled, the host has read access to all the regions of memory, however
      the host only has read and write access depending on a register

Annotation

Implementation Notes