Documentation/devicetree/bindings/mfd/aspeed-lpc.yaml

Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/mfd/aspeed-lpc.yaml

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System
Linux kernel
Corpus path
Documentation/devicetree/bindings/mfd/aspeed-lpc.yaml
Extension
.yaml
Size
5345 bytes
Lines
203
Domain
Support Tooling And Documentation
Bucket
Documentation
Inferred role
Support Tooling And Documentation: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

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Annotated Snippet

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# # Copyright (c) 2021 Aspeed Technology Inc.
%YAML 1.2
---
$id: http://devicetree.org/schemas/mfd/aspeed-lpc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Aspeed Low Pin Count (LPC) Bus Controller

maintainers:
  - Andrew Jeffery <andrew@aj.id.au>
  - Chia-Wei Wang <chiawei_wang@aspeedtech.com>

description:
  The LPC bus is a means to bridge a host CPU to a number of low-bandwidth
  peripheral devices, replacing the use of the ISA bus in the age of PCI[0]. The
  primary use case of the Aspeed LPC controller is as a slave on the bus
  (typically in a Baseboard Management Controller SoC), but under certain
  conditions it can also take the role of bus master.

  The LPC controller is represented as a multi-function device to account for the
  mix of functionality, which includes, but is not limited to

  * An IPMI Block Transfer[2] Controller

  * An LPC Host Interface Controller manages functions exposed to the host such
    as LPC firmware hub cycles, configuration of the LPC-to-AHB mapping, UART
    management and bus snoop configuration.

  * A set of SuperIO[3] scratch registers enabling implementation of e.g. custom
    hardware management protocols for handover between the host and baseboard
    management controller.

  Additionally the state of the LPC controller influences the pinmux
  configuration, therefore the host portion of the controller is exposed as a
  syscon as a means to arbitrate access.

properties:
  compatible:
    items:
      - enum:
          - aspeed,ast2400-lpc-v2
          - aspeed,ast2500-lpc-v2
          - aspeed,ast2600-lpc-v2
      - const: simple-mfd
      - const: syscon

  reg:
    maxItems: 1

  '#address-cells':
    const: 1

  '#size-cells':
    const: 1

  ranges: true

patternProperties:
  '^lpc-ctrl@[0-9a-f]+$':
    type: object
    additionalProperties: false

    description: |
      The LPC Host Interface Controller manages functions exposed to the host such as
      LPC firmware hub cycles, configuration of the LPC-to-AHB mapping, UART management
      and bus snoop configuration.

    properties:
      compatible:

Annotation

Implementation Notes