Documentation/devicetree/bindings/mfd/rohm,bd71847-pmic.yaml
Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/mfd/rohm,bd71847-pmic.yaml
File Facts
- System
- Linux kernel
- Corpus path
Documentation/devicetree/bindings/mfd/rohm,bd71847-pmic.yaml- Extension
.yaml- Size
- 7285 bytes
- Lines
- 229
- Domain
- Support Tooling And Documentation
- Bucket
- Documentation
- Inferred role
- Support Tooling And Documentation: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.
- Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.
Dependency Surface
dt-bindings/interrupt-controller/irq.h
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/mfd/rohm,bd71847-pmic.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ROHM BD71847 and BD71850 Power Management Integrated Circuit
maintainers:
- Matti Vaittinen <mazziesaccount@gmail.com>
description: |
BD71847AMWV and BD71850MWV are programmable Power Management ICs for powering
single-core, dual-core, and quad-core SoCs such as NXP-i.MX 8M. It is
optimized for low BOM cost and compact solution footprint. BD71847MWV and
BD71850MWV integrate 6 Buck regulators and 6 LDOs.
Datasheets are available at
https://www.rohm.com/products/power-management/power-management-ic-for-system/industrial-consumer-applications/nxp-imx/bd71847amwv-product
https://www.rohm.com/products/power-management/power-management-ic-for-system/industrial-consumer-applications/nxp-imx/bd71850mwv-product
properties:
compatible:
enum:
- rohm,bd71847
- rohm,bd71850
reg:
description:
I2C slave address.
maxItems: 1
interrupts:
maxItems: 1
clocks:
maxItems: 1
"#clock-cells":
const: 0
clock-output-names:
maxItems: 1
# The BD71847 abd BD71850 support two different HW states as reset target
# states. States are called as SNVS and READY. At READY state all the PMIC
# power outputs go down and OTP is reload. At the SNVS state all other logic
# and external devices apart from the SNVS power domain are shut off. Please
# refer to NXP i.MX8 documentation for further information regarding SNVS
# state. When a reset is done via SNVS state the PMIC OTP data is not reload.
# This causes power outputs that have been under SW control to stay down when
# reset has switched power state to SNVS. If reset is done via READY state the
# power outputs will be returned to HW control by OTP loading. Thus the reset
# target state is set to READY by default. If SNVS state is used the boot
# crucial regulators must have the regulator-always-on and regulator-boot-on
# properties set in regulator node.
rohm,reset-snvs-powered:
description:
Transfer PMIC to SNVS state at reset.
type: boolean
# Configure the "short press" and "long press" timers for the power button.
# Values are rounded to what hardware supports
# Short-press:
# Shortest being 10ms, next 500ms and then multiple of 500ms up to 7,5s
# Long-press:
# Shortest being 10ms, next 1000ms and then multiple of 1000ms up to 15s
# If these properties are not present the existing # configuration (from
# bootloader or OTP) is not touched.
Annotation
- Immediate include surface: `dt-bindings/interrupt-controller/irq.h`.
- Atlas domain: Support Tooling And Documentation / Documentation.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.