Documentation/devicetree/bindings/mips/img/xilfpga.txt

Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/mips/img/xilfpga.txt

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Linux kernel
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Documentation/devicetree/bindings/mips/img/xilfpga.txt
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.txt
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Support Tooling And Documentation
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Documentation
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Support Tooling And Documentation: documentation
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Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

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Imagination University Program MIPSfpga
=======================================

Under the Imagination University Program, a microAptiv UP core has been
released for academic usage.

As we are dealing with a MIPS core instantiated on an FPGA, specifications
are fluid and can be varied in RTL.

This binding document is provided as baseline guidance for the example
project provided by IMG.

The example project runs on the Nexys4DDR board by Digilent powered by
the ARTIX-7 FPGA by Xilinx.

Relevant details about the example project and the Nexys4DDR board:

- microAptiv UP core m14Kc
- 50MHz clock speed
- 128Mbyte DDR RAM	at 0x0000_0000
- 8Kbyte RAM		at 0x1000_0000
- axi_intc		at 0x1020_0000
- axi_uart16550		at 0x1040_0000
- axi_gpio		at 0x1060_0000
- axi_i2c		at 0x10A0_0000
- custom_gpio		at 0x10C0_0000
- axi_ethernetlite	at 0x10E0_0000
- 8Kbyte BootRAM	at 0x1FC0_0000

Required properties:
--------------------
 - compatible: Must include "digilent,nexys4ddr","img,xilfpga".

CPU nodes:
----------
A "cpus" node is required.  Required properties:
 - #address-cells: Must be 1.
 - #size-cells: Must be 0.
A CPU sub-node is also required for at least CPU 0. Required properties:
 - device_type: Must be "cpu".
 - compatible: Must be "mips,m14Kc".
 - reg: Must be <0>.
 - clocks: phandle to ext clock for fixed-clock received by MIPS core.

Example:

	compatible = "img,xilfpga","digilent,nexys4ddr";
	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "mips,m14Kc";
			reg = <0>;
			clocks	= <&ext>;
		};
	};

	ext: ext {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <50000000>;
	};

Boot protocol:
--------------

The BootRAM is a writeable "RAM" in FPGA at 0x1FC0_0000.
This is for easy reprogrammibility via JTAG.

Annotation

Implementation Notes