Documentation/devicetree/bindings/misc/pvpanic-mmio.txt

File Facts

System

Linux kernel

Corpus path

Documentation/devicetree/bindings/misc/pvpanic-mmio.txt

Extension

.txt

Size

700 bytes

Lines

30

Domain

Support Tooling And Documentation

Bucket

Documentation

Inferred role

Support Tooling And Documentation: documentation

Status

atlas-only

Why This File Exists

Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

• Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

Dependency Surface

• No C-style include directives detected by the generator.

Detected Declarations

• No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

QEMU's emulation / virtualization targets provide the following PVPANIC
MMIO Configuration interface on the "virt" machine.
type:

- a read-write, 16-bit wide data register.

QEMU exposes the data register to guests as memory mapped registers.

Required properties:

- compatible: "qemu,pvpanic-mmio".
- reg: the MMIO region used by the device.
  * Bytes 0x0  Write panic event to the reg when guest OS panics.
  * Bytes 0x1  Reserved.

Example:

/ {
        #size-cells = <0x2>;
        #address-cells = <0x2>;

        pvpanic-mmio@9060000 {
                compatible = "qemu,pvpanic-mmio";
                reg = <0x0 0x9060000 0x0 0x2>;
        };
};

Annotation

• Atlas domain: Support Tooling And Documentation / Documentation.
• Implementation status: atlas-only.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.