Documentation/devicetree/bindings/misc/xlnx,sd-fec.yaml

Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/misc/xlnx,sd-fec.yaml

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System
Linux kernel
Corpus path
Documentation/devicetree/bindings/misc/xlnx,sd-fec.yaml
Extension
.yaml
Size
4625 bytes
Lines
141
Domain
Support Tooling And Documentation
Bucket
Documentation
Inferred role
Support Tooling And Documentation: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/misc/xlnx,sd-fec.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Xilinx SDFEC(16nm) IP

maintainers:
  - Cvetic, Dragan <dragan.cvetic@amd.com>
  - Erim, Salih <salih.erim@amd.com>

description:
  The Soft Decision Forward Error Correction (SDFEC) Engine is a Hard IP block
  which provides high-throughput LDPC and Turbo Code implementations.
  The LDPC decode & encode functionality is capable of covering a range of
  customer specified Quasi-cyclic (QC) codes. The Turbo decode functionality
  principally covers codes used by LTE. The FEC Engine offers significant
  power and area savings versus implementations done in the FPGA fabric.

properties:
  compatible:
    const: xlnx,sd-fec-1.1

  reg:
    maxItems: 1

  clocks:
    minItems: 2
    maxItems: 8
    additionalItems: true
    items:
      - description: Main processing clock for processing core
      - description: AXI4-Lite memory-mapped slave interface clock
      - description: Control input AXI4-Stream Slave interface clock
      - description: DIN AXI4-Stream Slave interface clock
      - description: Status output AXI4-Stream Master interface clock
      - description: DOUT AXI4-Stream Master interface clock
      - description: DIN_WORDS AXI4-Stream Slave interface clock
      - description: DOUT_WORDS AXI4-Stream Master interface clock

  clock-names:
    allOf:
      - minItems: 2
        maxItems: 8
        additionalItems: true
        items:
          - const: core_clk
          - const: s_axi_aclk
      - items:
          enum:
            - core_clk
            - s_axi_aclk
            - s_axis_ctrl_aclk
            - s_axis_din_aclk
            - m_axis_status_aclk
            - m_axis_dout_aclk
            - s_axis_din_words_aclk
            - m_axis_dout_words_aclk

  interrupts:
    maxItems: 1

  xlnx,sdfec-code:
    description:
      The SD-FEC integrated block supports Low Density Parity Check (LDPC)
      decoding and encoding and Turbo code decoding. The LDPC codes used are
      highly configurable, and the specific code used can be specified on
      a codeword-by-codeword basis. The Turbo code decoding is required by LTE
      standard.

Annotation

Implementation Notes