Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml

Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml

File Facts

System: Linux kernel
Corpus path: Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml
Extension: .yaml
Size: 4216 bytes
Lines: 157
Domain: Support Tooling And Documentation
Bucket: Documentation
Inferred role: Support Tooling And Documentation: configuration, schema, or hardware description
Status: atlas-only

Why This File Exists

Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

Dependency Surface

No C-style include directives detected by the generator.

Detected Declarations

No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/mmc/cdns,sdhci.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Cadence SD/SDIO/eMMC Host Controller (SD4HC)

maintainers:
  - Masahiro Yamada <yamada.masahiro@socionext.com>

properties:
  compatible:
    items:
      - enum:
          - amd,pensando-elba-sd4hc
          - microchip,mpfs-sd4hc
          - microchip,pic64gx-sd4hc
          - mobileye,eyeq-sd4hc
          - socionext,uniphier-sd4hc
      - const: cdns,sd4hc

  reg:
    minItems: 1
    maxItems: 2

  interrupts:
    maxItems: 1

  clocks:
    maxItems: 1

  resets:
    maxItems: 1

  # PHY DLL input delays:
  # They are used to delay the data valid window, and align the window to
  # sampling clock. The delay starts from 5ns (for delay parameter equal to 0)
  # and it is increased by 2.5ns in each step.

  cdns,phy-input-delay-sd-highspeed:
    description: Value of the delay in the input path for SD high-speed timing
    $ref: /schemas/types.yaml#/definitions/uint32
    minimum: 0
    maximum: 0x1f

  cdns,phy-input-delay-legacy:
    description: Value of the delay in the input path for legacy timing
    $ref: /schemas/types.yaml#/definitions/uint32
    minimum: 0
    maximum: 0x1f

  cdns,phy-input-delay-sd-uhs-sdr12:
    description: Value of the delay in the input path for SD UHS SDR12 timing
    $ref: /schemas/types.yaml#/definitions/uint32
    minimum: 0
    maximum: 0x1f

  cdns,phy-input-delay-sd-uhs-sdr25:
    description: Value of the delay in the input path for SD UHS SDR25 timing
    $ref: /schemas/types.yaml#/definitions/uint32
    minimum: 0
    maximum: 0x1f

  cdns,phy-input-delay-sd-uhs-sdr50:
    description: Value of the delay in the input path for SD UHS SDR50 timing
    $ref: /schemas/types.yaml#/definitions/uint32
    minimum: 0
    maximum: 0x1f

Annotation

Atlas domain: Support Tooling And Documentation / Documentation.
Implementation status: atlas-only.

Implementation Notes

This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.