Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.yaml

Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.yaml

File Facts

System
Linux kernel
Corpus path
Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.yaml
Extension
.yaml
Size
2529 bytes
Lines
106
Domain
Support Tooling And Documentation
Bucket
Documentation
Inferred role
Support Tooling And Documentation: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

Dependency Surface

Detected Declarations

Annotated Snippet

# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/mmc/synopsys-dw-mshc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Synopsys Designware Mobile Storage Host Controller

maintainers:
  - Ulf Hansson <ulf.hansson@linaro.org>

# Everything else is described in the common file
properties:
  compatible:
    enum:
      - altr,socfpga-dw-mshc
      - img,pistachio-dw-mshc
      - snps,dw-mshc

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    minItems: 2
    maxItems: 2
    description:
      Handle to "biu" and "ciu" clocks for the
      bus interface unit clock and the card interface unit clock.

  clock-names:
    items:
      - const: biu
      - const: ciu

  iommus:
    maxItems: 1

  altr,sysmgr-syscon:
    $ref: /schemas/types.yaml#/definitions/phandle-array
    items:
      - items:
          - description: phandle to the sysmgr node
          - description: register offset that controls the SDMMC clock phase
          - description: register shift for the smplsel(drive in) setting
    description:
      This property is optional. Contains the phandle to System Manager block
      that contains the SDMMC clock-phase control register. The first value is
      the pointer to the sysmgr, the 2nd value is the register offset for the
      SDMMC clock phase register, and the 3rd value is the bit shift for the
      smplsel(drive in) setting.

allOf:
  - $ref: synopsys-dw-mshc-common.yaml#

  - if:
      properties:
        compatible:
          contains:
            const: altr,socfpga-dw-mshc
    then:
      properties:
        altr,sysmgr-syscon: true
    else:
      properties:
        iommus: false
        altr,sysmgr-syscon: false

Annotation

Implementation Notes