Documentation/devicetree/bindings/mtd/brcm,brcmnand.yaml

Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/mtd/brcm,brcmnand.yaml

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System
Linux kernel
Corpus path
Documentation/devicetree/bindings/mtd/brcm,brcmnand.yaml
Extension
.yaml
Size
8545 bytes
Lines
279
Domain
Support Tooling And Documentation
Bucket
Documentation
Inferred role
Support Tooling And Documentation: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

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Annotated Snippet

# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/mtd/brcm,brcmnand.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Broadcom STB NAND Controller

maintainers:
  - Brian Norris <computersforpeace@gmail.com>
  - Kamal Dasu <kdasu.kdev@gmail.com>
  - William Zhang <william.zhang@broadcom.com>

description: |
  The Broadcom Set-Top Box NAND controller supports low-level access to raw NAND
  flash chips. It has a memory-mapped register interface for both control
  registers and for its data input/output buffer. On some SoCs, this controller
  is paired with a custom DMA engine (inventively named "Flash DMA") which
  supports basic PROGRAM and READ functions, among other features.

  This controller was originally designed for STB SoCs (BCM7xxx) but is now
  available on a variety of Broadcom SoCs, including some BCM3xxx, MIPS based
  Broadband SoC (BCM63xx), ARM based Broadband SoC (BCMBCA) and iProc/Cygnus.
  Its history includes several similar (but not fully register compatible)
  versions.

  -- Additional SoC-specific NAND controller properties --

  The NAND controller is integrated differently on the variety of SoCs on which
  it is found. Part of this integration involves providing status and enable
  bits with which to control the 8 exposed NAND interrupts, as well as hardware
  for configuring the endianness of the data bus. On some SoCs, these features
  are handled via standard, modular components (e.g., their interrupts look like
  a normal IRQ chip), but on others, they are controlled in unique and
  interesting ways, sometimes with registers that lump multiple NAND-related
  functions together. The former case can be described simply by the standard
  interrupts properties in the main controller node. But for the latter
  exceptional cases, we define additional 'compatible' properties and associated
  register resources within the NAND controller node above.

properties:
  compatible:
    oneOf:
      - items:
          - enum:
              - brcm,brcmnand-v2.1
              - brcm,brcmnand-v2.2
              - brcm,brcmnand-v4.0
              - brcm,brcmnand-v5.0
              - brcm,brcmnand-v6.0
              - brcm,brcmnand-v6.1
              - brcm,brcmnand-v6.2
              - brcm,brcmnand-v7.0
              - brcm,brcmnand-v7.1
              - brcm,brcmnand-v7.2
              - brcm,brcmnand-v7.3
          - const: brcm,brcmnand
      - description: BCMBCA SoC-specific NAND controller
        items:
          - const: brcm,nand-bcm63138
          - enum:
              - brcm,brcmnand-v7.0
              - brcm,brcmnand-v7.1
          - const: brcm,brcmnand
      - description: iProc SoC-specific NAND controller
        items:
          - const: brcm,nand-iproc
          - const: brcm,brcmnand-v6.1
      - description: BCM63168 SoC-specific NAND controller
        items:

Annotation

Implementation Notes