Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml

Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml

File Facts

System
Linux kernel
Corpus path
Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml
Extension
.yaml
Size
21935 bytes
Lines
848
Domain
Support Tooling And Documentation
Bucket
Documentation
Inferred role
Support Tooling And Documentation: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

Dependency Surface

Detected Declarations

Annotated Snippet

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/dsa/mediatek,mt7530.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Mediatek MT7530 and MT7531 Ethernet Switches

maintainers:
  - Arınç ÜNAL <arinc.unal@arinc9.com>
  - Landen Chao <Landen.Chao@mediatek.com>
  - DENG Qingfang <dqfext@gmail.com>
  - Sean Wang <sean.wang@mediatek.com>
  - Daniel Golle <daniel@makrotopia.org>

description: |
  There are three versions of MT7530, standalone, in a multi-chip module and
  built-into a SoC.

  MT7530 is a part of the multi-chip module in MT7620AN, MT7620DA, MT7620DAN,
  MT7620NN, MT7621AT, MT7621DAT, MT7621ST and MT7623AI SoCs.

  The MT7988 SoC comes with a built-in switch similar to MT7531 as well as four
  Gigabit Ethernet PHYs. The switch registers are directly mapped into the SoC's
  memory map rather than using MDIO. The switch has an internally connected 10G
  CPU port and 4 user ports connected to the built-in Gigabit Ethernet PHYs.

  The MT7530 in MT7620AN, MT7620DA, MT7620DAN and MT7620NN SoCs has 10/100 PHYs
  and the switch registers are directly mapped into SoC's memory map rather than
  using MDIO. The DSA driver currently doesn't support MT7620 variants.

  There is only the standalone version of MT7531.

  Port 5 on MT7530 supports various configurations:

    - Port 5 can be used as a CPU port.

    - PHY 0 or 4 of the switch can be muxed to gmac5 of the switch. Therefore,
      the gmac of the SoC which is wired to port 5 can connect to the PHY.
      This is usually used for connecting the wan port directly to the CPU to
      achieve 2 Gbps routing in total.

      The driver looks up the reg on the ethernet-phy node, which the phy-handle
      property on the gmac node refers to, to mux the specified phy.

      The driver requires the gmac of the SoC to have "mediatek,eth-mac" as the
      compatible string and the reg must be 1. So, for now, only gmac1 of a
      MediaTek SoC can benefit this. Banana Pi BPI-R2 suits this.

      For the MT7621 SoCs, rgmii2 group must be claimed with rgmii2 function.

      Check out example 5.

    - For the multi-chip module MT7530, in case of an external phy wired to
      gmac1 of the SoC, port 5 must not be enabled.

      In case of muxing PHY 0 or 4, the external phy must not be enabled.

      For the MT7621 SoCs, rgmii2 group must be claimed with rgmii2 function.

      Check out example 6.

    - Port 5 can be wired to an external phy. Port 5 becomes a DSA user port.

      For the multi-chip module MT7530, the external phy must be wired TX to TX
      to gmac1 of the SoC for this to work. Ubiquiti EdgeRouter X SFP is wired
      this way.

      For the multi-chip module MT7530, muxing PHY 0 or 4 won't work when the
      external phy is connected TX to TX.

Annotation

Implementation Notes