Documentation/devicetree/bindings/net/dsa/nxp,sja1105.yaml

Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/net/dsa/nxp,sja1105.yaml

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Linux kernel
Corpus path
Documentation/devicetree/bindings/net/dsa/nxp,sja1105.yaml
Extension
.yaml
Size
6393 bytes
Lines
211
Domain
Support Tooling And Documentation
Bucket
Documentation
Inferred role
Support Tooling And Documentation: configuration, schema, or hardware description
Status
atlas-only

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Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/dsa/nxp,sja1105.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NXP SJA1105 Automotive Ethernet Switch Family

description:
  The SJA1105 SPI interface requires a CS-to-CLK time (t2 in UM10944.pdf) of at
  least one half of t_CLK. At an SPI frequency of 1MHz, this means a minimum
  cs_sck_delay of 500ns. Ensuring that this SPI timing requirement is observed
  depends on the SPI bus master driver.

maintainers:
  - Vladimir Oltean <vladimir.oltean@nxp.com>

properties:
  compatible:
    enum:
      - nxp,sja1105e
      - nxp,sja1105t
      - nxp,sja1105p
      - nxp,sja1105q
      - nxp,sja1105r
      - nxp,sja1105s
      - nxp,sja1110a
      - nxp,sja1110b
      - nxp,sja1110c
      - nxp,sja1110d

  reg:
    maxItems: 1

  reset-gpios:
    description:
      A GPIO connected to the active-low RST_N pin of the SJA1105. Note that
      reset of this chip is performed via SPI and the RST_N pin must be wired
      to satisfy the power-up sequence documented in "SJA1105PQRS Application
      Hints" (AH1704) sec. 2.4.4. Connecting the SJA1105 RST_N pin to a GPIO is
      therefore discouraged.
    maxItems: 1

  clocks:
    maxItems: 1

  spi-cpha: true
  spi-cpol: true

  # Optional container node for the 2 internal MDIO buses of the SJA1110
  # (one for the internal 100base-T1 PHYs and the other for the single
  # 100base-TX PHY). The "reg" property does not have physical significance.
  # The PHY addresses to port correspondence is as follows: for 100base-T1,
  # port 5 has PHY 1, port 6 has PHY 2 etc, while for 100base-TX, port 1 has
  # PHY 1.
  mdios:
    type: object
    additionalProperties: false

    properties:
      '#address-cells':
        const: 1
      '#size-cells':
        const: 0

    patternProperties:
      "^mdio@[0-1]$":
        $ref: /schemas/net/mdio.yaml#
        unevaluatedProperties: false

Annotation

Implementation Notes