Documentation/devicetree/bindings/net/microchip,sparx5-switch.yaml
Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/net/microchip,sparx5-switch.yaml
File Facts
- System
- Linux kernel
- Corpus path
Documentation/devicetree/bindings/net/microchip,sparx5-switch.yaml- Extension
.yaml- Size
- 7793 bytes
- Lines
- 283
- Domain
- Support Tooling And Documentation
- Bucket
- Documentation
- Inferred role
- Support Tooling And Documentation: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.
- Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.
Dependency Surface
dt-bindings/interrupt-controller/arm-gic.h
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/microchip,sparx5-switch.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Microchip Sparx5 Ethernet switch controller
maintainers:
- Steen Hegelund <steen.hegelund@microchip.com>
- Lars Povlsen <lars.povlsen@microchip.com>
- Daniel Machon <daniel.machon@microchip.com>
description: |
The SparX-5 Enterprise Ethernet switch family provides a rich set of
Enterprise switching features such as advanced TCAM-based VLAN and
QoS processing enabling delivery of differentiated services, and
security through TCAM-based frame processing using versatile content
aware processor (VCAP).
IPv4/IPv6 Layer 3 (L3) unicast and multicast routing is supported
with up to 18K IPv4/9K IPv6 unicast LPM entries and up to 9K IPv4/3K
IPv6 (S,G) multicast groups.
L3 security features include source guard and reverse path
forwarding (uRPF) tasks. Additional L3 features include VRF-Lite and
IP tunnels (IP over GRE/IP).
The SparX-5 switch family targets managed Layer 2 and Layer 3
equipment in SMB, SME, and Enterprise where high port count
1G/2.5G/5G/10G switching with 10G/25G aggregation links is required.
properties:
$nodename:
pattern: "^switch@[0-9a-f]+$"
compatible:
oneOf:
- enum:
- microchip,lan9691-switch
- microchip,sparx5-switch
- items:
- enum:
- microchip,lan969c-switch
- microchip,lan969b-switch
- microchip,lan969a-switch
- microchip,lan9699-switch
- microchip,lan9698-switch
- microchip,lan9697-switch
- microchip,lan9696-switch
- microchip,lan9695-switch
- microchip,lan9694-switch
- microchip,lan9693-switch
- microchip,lan9692-switch
- const: microchip,lan9691-switch
reg:
minItems: 2
items:
- description: cpu target
- description: devices target
- description: general control block target
reg-names:
minItems: 2
items:
- const: cpu
- const: devices
- const: gcb
Annotation
- Immediate include surface: `dt-bindings/interrupt-controller/arm-gic.h`.
- Atlas domain: Support Tooling And Documentation / Documentation.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.