Documentation/devicetree/bindings/net/nxp,s32-dwmac.yaml

Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/net/nxp,s32-dwmac.yaml

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System
Linux kernel
Corpus path
Documentation/devicetree/bindings/net/nxp,s32-dwmac.yaml
Extension
.yaml
Size
4727 bytes
Lines
156
Domain
Support Tooling And Documentation
Bucket
Documentation
Inferred role
Support Tooling And Documentation: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

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Annotated Snippet

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright 2021-2026 NXP
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/nxp,s32-dwmac.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NXP S32G2xx/S32G3xx/S32R45 GMAC ethernet controller

maintainers:
  - Jan Petrous (OSS) <jan.petrous@oss.nxp.com>

description:
  This device is a Synopsys DWC IP, integrated on NXP S32G/R SoCs.
  The SoC series S32G2xx and S32G3xx feature one DWMAC instance,
  the SoC S32R45 has two instances. The devices can use RGMII/RMII/MII
  interface over Pinctrl device or the output can be routed
  to the embedded SerDes for SGMII connectivity.
  The DWMAC instances have connected all RX/TX queues interrupts,
  enabling load balancing of data traffic across all CPU cores.

properties:
  compatible:
    oneOf:
      - const: nxp,s32g2-dwmac
      - items:
          - enum:
              - nxp,s32g3-dwmac
              - nxp,s32r45-dwmac
          - const: nxp,s32g2-dwmac

  reg:
    items:
      - description: Main GMAC registers
      - description: GMAC PHY mode control register

  nxp,phy-sel:
    $ref: /schemas/types.yaml#/definitions/phandle-array
    items:
      - items:
          - description: phandle to the GPR syscon node
          - description: offset of PHY selection register
    description:
      This phandle points to the GMAC_0_CTRL_STS register which controls the
      GMAC_0 configuration options.  The register lets you select the PHY
      interface and the PHY mode.  It also controls if the FTM_0 or FTM_1
      FlexTimer Modules connect to GMAC_0.

  interrupts:
    minItems: 1
    maxItems: 11

  interrupt-names:
    oneOf:
      - items:
          - const: macirq
      - items:
          - const: macirq
          - const: tx-queue-0
          - const: rx-queue-0
          - const: tx-queue-1
          - const: rx-queue-1
          - const: tx-queue-2
          - const: rx-queue-2
          - const: tx-queue-3
          - const: rx-queue-3
          - const: tx-queue-4
          - const: rx-queue-4

  clocks:

Annotation

Implementation Notes