Documentation/devicetree/bindings/net/qca,ar803x.yaml

Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/net/qca,ar803x.yaml

File Facts

System
Linux kernel
Corpus path
Documentation/devicetree/bindings/net/qca,ar803x.yaml
Extension
.yaml
Size
5117 bytes
Lines
197
Domain
Support Tooling And Documentation
Bucket
Documentation
Inferred role
Support Tooling And Documentation: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

Dependency Surface

Detected Declarations

Annotated Snippet

# SPDX-License-Identifier: GPL-2.0+
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/qca,ar803x.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Atheros AR803x PHY

maintainers:
  - Andrew Lunn <andrew@lunn.ch>
  - Florian Fainelli <f.fainelli@gmail.com>
  - Heiner Kallweit <hkallweit1@gmail.com>

description: |
  Bindings for Qualcomm Atheros AR803x PHYs

allOf:
  - $ref: ethernet-phy.yaml#
  - if:
      properties:
        compatible:
          contains:
            enum:
              - ethernet-phy-id004d.d0c0

    then:
      properties:
        reg:
          const: 7  # This PHY is always at MDIO address 7 in the IPQ5018 SoC

        clocks:
          items:
            - description: RX clock
            - description: TX clock

        clock-names:
          items:
            - const: rx
            - const: tx

        resets:
          items:
            - description:
                GE PHY MISC reset which triggers a reset across MDC, DSP, RX, and TX lines.

        qcom,dac-preset-short-cable:
          description:
            Set if this phy is connected to another phy to adjust the values for
            MDAC and EDAC to adjust amplitude, bias current settings, and error
            detection and correction algorithm to accommodate for short cable length.
            If not set, DAC values are not modified and it is assumed the MDI output pins
            of this PHY are directly connected to an RJ45 connector.
          type: boolean

      required:
        - clocks
        - clock-names
        - resets

properties:
  compatible:
    enum:
      - ethernet-phy-id004d.d0c0

  qca,clk-out-frequency:
    description: Clock output frequency in Hertz.
    $ref: /schemas/types.yaml#/definitions/uint32
    enum: [25000000, 50000000, 62500000, 125000000]

  qca,clk-out-strength:

Annotation

Implementation Notes