Documentation/devicetree/bindings/net/qcom,ipq9574-ppe.yaml

Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/net/qcom,ipq9574-ppe.yaml

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Documentation/devicetree/bindings/net/qcom,ipq9574-ppe.yaml
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.yaml
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Support Tooling And Documentation
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Documentation
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Support Tooling And Documentation: configuration, schema, or hardware description
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# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/qcom,ipq9574-ppe.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm IPQ packet process engine (PPE)

maintainers:
  - Luo Jie <quic_luoj@quicinc.com>
  - Lei Wei <quic_leiwei@quicinc.com>
  - Suruchi Agarwal <quic_suruchia@quicinc.com>
  - Pavithra R <quic_pavir@quicinc.com>

description: |
  The Ethernet functionality in the PPE (Packet Process Engine) is comprised
  of three components, the switch core, port wrapper and Ethernet DMA.

  The Switch core in the IPQ9574 PPE has maximum of 6 front panel ports and
  two FIFO interfaces. One of the two FIFO interfaces is used for Ethernet
  port to host CPU communication using Ethernet DMA. The other is used
  communicating to the EIP engine which is used for IPsec offload. On the
  IPQ9574, the PPE includes 6 GMAC/XGMACs that can be connected with external
  Ethernet PHY. Switch core also includes BM (Buffer Management), QM (Queue
  Management) and SCH (Scheduler) modules for supporting the packet processing.

  The port wrapper provides connections from the 6 GMAC/XGMACS to UNIPHY (PCS)
  supporting various modes such as SGMII/QSGMII/PSGMII/USXGMII/10G-BASER. There
  are 3 UNIPHY (PCS) instances supported on the IPQ9574.

  Ethernet DMA is used to transmit and receive packets between the six Ethernet
  ports and ARM host CPU.

  The follow diagram shows the PPE hardware block along with its connectivity
  to the external hardware blocks such clock hardware blocks (CMNPLL, GCC,
  NSS clock controller) and Ethernet PCS/PHY blocks. For depicting the PHY
  connectivity, one 4x1 Gbps PHY (QCA8075) and two 10 GBps PHYs are used as an
  example.

           +---------+
           |  48 MHZ |
           +----+----+
                |(clock)
                v
           +----+----+
    +------| CMN PLL |
    |      +----+----+
    |           |(clock)
    |           v
    |      +----+----+           +----+----+  (clock) +----+----+
    |  +---|  NSSCC  |           |   GCC   |--------->|   MDIO  |
    |  |   +----+----+           +----+----+          +----+----+
    |  |        |(clock & reset)      |(clock)
    |  |        v                     v
    |  |   +----+---------------------+--+----------+----------+---------+
    |  |   |       +-----+               |EDMA FIFO |          | EIP FIFO|
    |  |   |       | SCH |               +----------+          +---------+
    |  |   |       +-----+                        |              |       |
    |  |   |  +------+   +------+               +-------------------+    |
    |  |   |  |  BM  |   |  QM  |  IPQ9574-PPE  |    L2/L3 Process  |    |
    |  |   |  +------+   +------+               +-------------------+    |
    |  |   |                                             |               |
    |  |   | +-------+ +-------+ +-------+ +-------+ +-------+ +-------+ |
    |  |   | |  MAC0 | |  MAC1 | |  MAC2 | |  MAC3 | | XGMAC4| |XGMAC5 | |
    |  |   | +---+---+ +---+---+ +---+---+ +---+---+ +---+---+ +---+---+ |
    |  |   |     |         |         |         |         |         |     |
    |  |   +-----+---------+---------+---------+---------+---------+-----+
    |  |         |         |         |         |         |         |
    |  |     +---+---------+---------+---------+---+ +---+---+ +---+---+
    +--+---->|                PCS0                 | |  PCS1 | | PCS2  |

Annotation

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