Documentation/devicetree/bindings/pci/altr,pcie-root-port.yaml
Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/pci/altr,pcie-root-port.yaml
File Facts
- System
- Linux kernel
- Corpus path
Documentation/devicetree/bindings/pci/altr,pcie-root-port.yaml- Extension
.yaml- Size
- 3120 bytes
- Lines
- 124
- Domain
- Support Tooling And Documentation
- Bucket
- Documentation
- Inferred role
- Support Tooling And Documentation: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.
- Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.
Dependency Surface
dt-bindings/interrupt-controller/arm-gic.hdt-bindings/interrupt-controller/irq.h
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
# Copyright (C) 2015, 2019, 2024, Intel Corporation
%YAML 1.2
---
$id: http://devicetree.org/schemas/altr,pcie-root-port.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Altera PCIe Root Port
maintainers:
- Matthew Gerlach <matthew.gerlach@linux.intel.com>
properties:
compatible:
description: Each family of socfpga has its own implementation of the
PCI controller. The altr,pcie-root-port-1.0 is used for the Cyclone5
family of chips. The Stratix10 family of chips is supported by the
altr,pcie-root-port-2.0. The Agilex family of chips has three,
non-register compatible, variants of PCIe Hard IP referred to as the
F-Tile, P-Tile, and R-Tile, depending on the specific chip instance.
enum:
- altr,pcie-root-port-1.0
- altr,pcie-root-port-2.0
- altr,pcie-root-port-3.0-f-tile
- altr,pcie-root-port-3.0-p-tile
- altr,pcie-root-port-3.0-r-tile
reg:
items:
- description: TX slave port region
- description: Control register access region
- description: Hard IP region
minItems: 2
reg-names:
items:
- const: Txs
- const: Cra
- const: Hip
minItems: 2
interrupts:
maxItems: 1
interrupt-controller: true
interrupt-map-mask:
items:
- const: 0
- const: 0
- const: 0
- const: 7
interrupt-map:
maxItems: 4
"#interrupt-cells":
const: 1
msi-parent: true
required:
- compatible
- reg
- reg-names
- interrupts
- "#interrupt-cells"
- interrupt-controller
- interrupt-map
Annotation
- Immediate include surface: `dt-bindings/interrupt-controller/arm-gic.h`, `dt-bindings/interrupt-controller/irq.h`.
- Atlas domain: Support Tooling And Documentation / Documentation.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.