Documentation/devicetree/bindings/pci/amazon,al-alpine-v3-pcie.yaml
Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/pci/amazon,al-alpine-v3-pcie.yaml
File Facts
- System
- Linux kernel
- Corpus path
Documentation/devicetree/bindings/pci/amazon,al-alpine-v3-pcie.yaml- Extension
.yaml- Size
- 1799 bytes
- Lines
- 72
- Domain
- Support Tooling And Documentation
- Bucket
- Documentation
- Inferred role
- Support Tooling And Documentation: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.
- Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.
Dependency Surface
dt-bindings/interrupt-controller/arm-gic.h
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pci/amazon,al-alpine-v3-pcie.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Amazon Annapurna Labs Alpine v3 PCIe Host Bridge
maintainers:
- Jonathan Chocron <jonnyc@amazon.com>
description:
Amazon's Annapurna Labs PCIe Host Controller is based on the Synopsys
DesignWare PCI controller.
allOf:
- $ref: snps,dw-pcie.yaml#
properties:
compatible:
enum:
- amazon,al-alpine-v2-pcie
- amazon,al-alpine-v3-pcie
reg:
items:
- description: PCIe ECAM space
- description: AL proprietary registers
- description: Designware PCIe registers
reg-names:
items:
- const: config
- const: controller
- const: dbi
interrupts:
maxItems: 1
unevaluatedProperties: false
required:
- compatible
- reg
- reg-names
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
bus {
#address-cells = <2>;
#size-cells = <2>;
pcie@fb600000 {
compatible = "amazon,al-alpine-v3-pcie";
reg = <0x0 0xfb600000 0x0 0x00100000
0x0 0xfd800000 0x0 0x00010000
0x0 0xfd810000 0x0 0x00001000>;
reg-names = "config", "controller", "dbi";
bus-range = <0 255>;
device_type = "pci";
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
interrupt-map-mask = <0x00 0 0 7>;
interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; /* INTa */
ranges = <0x02000000 0x0 0xc0010000 0x0 0xc0010000 0x0 0x07ff0000>;
};
Annotation
- Immediate include surface: `dt-bindings/interrupt-controller/arm-gic.h`.
- Atlas domain: Support Tooling And Documentation / Documentation.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.