Documentation/devicetree/bindings/pci/aspeed,ast2600-pcie.yaml

Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/pci/aspeed,ast2600-pcie.yaml

File Facts

System
Linux kernel
Corpus path
Documentation/devicetree/bindings/pci/aspeed,ast2600-pcie.yaml
Extension
.yaml
Size
4378 bytes
Lines
183
Domain
Support Tooling And Documentation
Bucket
Documentation
Inferred role
Support Tooling And Documentation: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

Dependency Surface

Detected Declarations

Annotated Snippet

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pci/aspeed,ast2600-pcie.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: ASPEED PCIe Root Complex Controller

maintainers:
  - Jacky Chou <jacky_chou@aspeedtech.com>

description:
  The ASPEED PCIe Root Complex controller provides PCI Express Root Complex
  functionality for ASPEED SoCs, such as the AST2600 and AST2700.
  This controller enables connectivity to PCIe endpoint devices, supporting
  memory and I/O windows, MSI and INTx interrupts, and integration with
  the SoC's clock, reset, and pinctrl subsystems. On AST2600, the PCIe Root
  Port device number is always 8.

properties:
  compatible:
    enum:
      - aspeed,ast2600-pcie
      - aspeed,ast2700-pcie

  reg:
    maxItems: 1

  ranges:
    minItems: 2
    maxItems: 2

  interrupts:
    maxItems: 1
    description: INTx and MSI interrupt

  resets:
    items:
      - description: PCIe controller reset

  reset-names:
    items:
      - const: h2x

  aspeed,ahbc:
    $ref: /schemas/types.yaml#/definitions/phandle
    description:
      Phandle to the ASPEED AHB Controller (AHBC) syscon node.
      This reference is used by the PCIe controller to access
      system-level configuration registers related to the AHB bus.
      To enable AHB access for the PCIe controller.

  aspeed,pciecfg:
    $ref: /schemas/types.yaml#/definitions/phandle
    description:
      Phandle to the ASPEED PCIe configuration syscon node.
      This reference allows the PCIe controller to access
      SoC-specific PCIe configuration registers. There are the others
      functions such PCIe RC and PCIe EP will use this common register
      to configure the SoC interfaces.

  interrupt-controller: true

patternProperties:
  "^pcie@[0-9a-f]+,0$":
    type: object
    $ref: /schemas/pci/pci-pci-bridge.yaml#

    properties:
      reg:

Annotation

Implementation Notes