Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml
Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml
File Facts
- System
- Linux kernel
- Corpus path
Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml- Extension
.yaml- Size
- 4919 bytes
- Lines
- 202
- Domain
- Support Tooling And Documentation
- Bucket
- Documentation
- Inferred role
- Support Tooling And Documentation: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.
- Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.
Dependency Surface
dt-bindings/clock/imx8mp-clock.hdt-bindings/power/imx8mp-power.hdt-bindings/reset/imx8mp-reset.hdt-bindings/interrupt-controller/arm-gic.h
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pci/fsl,imx6q-pcie-ep.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale i.MX6 PCIe Endpoint controller
maintainers:
- Lucas Stach <l.stach@pengutronix.de>
- Richard Zhu <hongxing.zhu@nxp.com>
description: |+
This PCIe controller is based on the Synopsys DesignWare PCIe IP and
thus inherits all the common properties defined in snps,dw-pcie-ep.yaml.
The controller instances are dual mode where in they can work either in
Root Port mode or Endpoint mode but one at a time.
properties:
compatible:
oneOf:
- enum:
- fsl,imx8mm-pcie-ep
- fsl,imx8mp-pcie-ep
- fsl,imx8mq-pcie-ep
- fsl,imx8q-pcie-ep
- fsl,imx95-pcie-ep
- items:
- enum:
- fsl,imx94-pcie-ep
- fsl,imx943-pcie-ep
- const: fsl,imx95-pcie-ep
clocks:
minItems: 3
items:
- description: PCIe bridge clock.
- description: PCIe bus clock.
- description: PCIe PHY clock.
- description: Additional required clock entry for imx6sx-pcie,
imx6sx-pcie-ep, imx8mq-pcie, imx8mq-pcie-ep.
clock-names:
minItems: 3
maxItems: 4
interrupts:
items:
- description: builtin eDMA interrupter.
interrupt-names:
items:
- const: dma
required:
- compatible
- reg
- reg-names
- interrupts
- interrupt-names
allOf:
- $ref: /schemas/pci/snps,dw-pcie-ep.yaml#
- $ref: /schemas/pci/fsl,imx6q-pcie-common.yaml#
- if:
properties:
compatible:
enum:
- fsl,imx8mm-pcie-ep
- fsl,imx8mq-pcie-ep
Annotation
- Immediate include surface: `dt-bindings/clock/imx8mp-clock.h`, `dt-bindings/power/imx8mp-power.h`, `dt-bindings/reset/imx8mp-reset.h`, `dt-bindings/interrupt-controller/arm-gic.h`.
- Atlas domain: Support Tooling And Documentation / Documentation.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.