Documentation/devicetree/bindings/pci/fsl,layerscape-pcie.yaml

Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/pci/fsl,layerscape-pcie.yaml

File Facts

System
Linux kernel
Corpus path
Documentation/devicetree/bindings/pci/fsl,layerscape-pcie.yaml
Extension
.yaml
Size
4733 bytes
Lines
183
Domain
Support Tooling And Documentation
Bucket
Documentation
Inferred role
Support Tooling And Documentation: configuration, schema, or hardware description
Status
atlas-only

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Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

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Annotated Snippet

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pci/fsl,layerscape-pcie.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Freescale Layerscape PCIe Root Complex(RC) controller

maintainers:
  - Frank Li <Frank.Li@nxp.com>

description:
  This PCIe RC controller is based on the Synopsys DesignWare PCIe IP

  This controller derives its clocks from the Reset Configuration Word (RCW)
  which is used to describe the PLL settings at the time of chip-reset.

  Also as per the available Reference Manuals, there is no specific 'version'
  register available in the Freescale PCIe controller register set,
  which can allow determining the underlying DesignWare PCIe controller version
  information.

properties:
  compatible:
    oneOf:
      - enum:
          - fsl,ls1012a-pcie
          - fsl,ls1021a-pcie
          - fsl,ls1028a-pcie
          - fsl,ls1043a-pcie
          - fsl,ls1046a-pcie
          - fsl,ls1088a-pcie
          - fsl,ls2080a-pcie
          - fsl,ls2085a-pcie
          - fsl,ls2088a-pcie
      - items:
          - const: fsl,lx2160ar2-pcie
          - const: fsl,ls2088a-pcie
  reg:
    maxItems: 2

  reg-names:
    items:
      - const: regs
      - const: config

  fsl,pcie-scfg:
    $ref: /schemas/types.yaml#/definitions/phandle-array
    description: A phandle to the SCFG device node. The second entry is the
      physical PCIe controller index starting from '0'. This is used to get
      SCFG PEXN registers.
    items:
      items:
        - description: A phandle to the SCFG device node
        - description: PCIe controller index starting from '0'
    maxItems: 1

  big-endian:
    $ref: /schemas/types.yaml#/definitions/flag
    description: If the PEX_LUT and PF register block is in big-endian, specify
      this property.

  dma-coherent: true

  msi-parent: true

  iommu-map: true

  interrupts:
    minItems: 1

Annotation

Implementation Notes