Documentation/devicetree/bindings/pci/marvell,kirkwood-pcie.yaml

Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/pci/marvell,kirkwood-pcie.yaml

File Facts

System
Linux kernel
Corpus path
Documentation/devicetree/bindings/pci/marvell,kirkwood-pcie.yaml
Extension
.yaml
Size
10498 bytes
Lines
281
Domain
Support Tooling And Documentation
Bucket
Documentation
Inferred role
Support Tooling And Documentation: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

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Annotated Snippet

# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/pci/marvell,kirkwood-pcie.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Marvell EBU PCIe interfaces

maintainers:
  - Thomas Petazzoni <thomas.petazzoni@bootlin.com>
  - Pali Rohár <pali@kernel.org>

allOf:
  - $ref: /schemas/pci/pci-host-bridge.yaml#

properties:
  compatible:
    enum:
      - marvell,armada-370-pcie
      - marvell,armada-xp-pcie
      - marvell,dove-pcie
      - marvell,kirkwood-pcie

  ranges:
    description: >
      The ranges describing the MMIO registers have the following layout:

        0x82000000 0 r MBUS_ID(0xf0, 0x01) r 0 s

      where:

        * r is a 32-bits value that gives the offset of the MMIO registers of
        this PCIe interface, from the base of the internal registers.

        * s is a 32-bits value that give the size of this MMIO registers area.
        This range entry translates the '0x82000000 0 r' PCI address into the
        'MBUS_ID(0xf0, 0x01) r' CPU address, which is part of the internal
        register window (as identified by MBUS_ID(0xf0, 0x01)).

      The ranges describing the MBus windows have the following layout:

          0x8t000000 s 0     MBUS_ID(w, a) 0 1 0

      where:

        * t is the type of the MBus window (as defined by the standard PCI DT
        bindings), 1 for I/O and 2 for memory.

        * s is the PCI slot that corresponds to this PCIe interface

        * w is the 'target ID' value for the MBus window

        * a the 'attribute' value for the MBus window.

      Since the location and size of the different MBus windows is not fixed in
      hardware, and only determined in runtime, those ranges cover the full first
      4 GB of the physical address space, and do not translate into a valid CPU
      address.

  msi-parent:
    maxItems: 1

patternProperties:
  '^pcie@':
    type: object
    allOf:
      - $ref: /schemas/pci/pci-bus-common.yaml#
      - $ref: /schemas/pci/pci-device.yaml#
    unevaluatedProperties: false

Annotation

Implementation Notes