Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.yaml
Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.yaml
File Facts
- System
- Linux kernel
- Corpus path
Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.yaml- Extension
.yaml- Size
- 11765 bytes
- Lines
- 385
- Domain
- Support Tooling And Documentation
- Bucket
- Documentation
- Inferred role
- Support Tooling And Documentation: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.
- Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
Dependency Surface
dt-bindings/clock/tegra194-clock.hdt-bindings/interrupt-controller/arm-gic.hdt-bindings/power/tegra194-powergate.hdt-bindings/reset/tegra194-reset.hdt-bindings/clock/tegra234-clock.hdt-bindings/power/tegra234-powergate.hdt-bindings/reset/tegra234-reset.h
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pci/nvidia,tegra194-pcie.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA Tegra194 (and later) PCIe controller (Synopsys DesignWare Core based)
maintainers:
- Thierry Reding <thierry.reding@gmail.com>
- Jon Hunter <jonathanh@nvidia.com>
- Vidya Sagar <vidyas@nvidia.com>
description: |
This PCIe controller is based on the Synopsys DesignWare PCIe IP and thus
inherits all the common properties defined in snps,dw-pcie.yaml. Some of
the controller instances are dual mode where in they can work either in
Root Port mode or Endpoint mode but one at a time.
See nvidia,tegra194-pcie-ep.yaml for details on the Endpoint mode device
tree bindings.
properties:
compatible:
enum:
- nvidia,tegra194-pcie
- nvidia,tegra234-pcie
reg:
minItems: 4
items:
- description: controller's application logic registers
- description: configuration registers
- description: iATU and DMA registers. This is where the iATU (internal
Address Translation Unit) registers of the PCIe core are made
available for software access.
- description: aperture where the Root Port's own configuration
registers are available.
- description: aperture to access the configuration space through ECAM.
reg-names:
minItems: 4
items:
- const: appl
- const: config
- const: atu_dma
- const: dbi
- const: ecam
interrupts:
items:
- description: controller interrupt
- description: MSI interrupt
interrupt-names:
items:
- const: intr
- const: msi
clocks:
minItems: 1
items:
- description: core clock
- description: monitor clock
clock-names:
minItems: 1
items:
- const: core
- const: core_m
Annotation
- Immediate include surface: `dt-bindings/clock/tegra194-clock.h`, `dt-bindings/interrupt-controller/arm-gic.h`, `dt-bindings/power/tegra194-powergate.h`, `dt-bindings/reset/tegra194-reset.h`, `dt-bindings/clock/tegra234-clock.h`, `dt-bindings/power/tegra234-powergate.h`, `dt-bindings/reset/tegra234-reset.h`.
- Atlas domain: Support Tooling And Documentation / Documentation.
- Implementation status: atlas-only.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.