Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt

Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt

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System
Linux kernel
Corpus path
Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt
Extension
.txt
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20697 bytes
Lines
671
Domain
Support Tooling And Documentation
Bucket
Documentation
Inferred role
Support Tooling And Documentation: documentation
Status
atlas-only

Why This File Exists

Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

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Annotated Snippet

NVIDIA Tegra PCIe controller

Required properties:
- compatible: Must be:
  - "nvidia,tegra20-pcie": for Tegra20
  - "nvidia,tegra30-pcie": for Tegra30
  - "nvidia,tegra124-pcie": for Tegra124 and Tegra132
  - "nvidia,tegra210-pcie": for Tegra210
  - "nvidia,tegra186-pcie": for Tegra186
- power-domains: To ungate power partition by BPMP powergate driver. Must
  contain BPMP phandle and PCIe power partition ID. This is required only
  for Tegra186.
- device_type: Must be "pci"
- reg: A list of physical base address and length for each set of controller
  registers. Must contain an entry for each entry in the reg-names property.
- reg-names: Must include the following entries:
  "pads": PADS registers
  "afi": AFI registers
  "cs": configuration space region
- interrupts: A list of interrupt outputs of the controller. Must contain an
  entry for each entry in the interrupt-names property.
- interrupt-names: Must include the following entries:
  "intr": The Tegra interrupt that is asserted for controller interrupts
  "msi": The Tegra interrupt that is asserted when an MSI is received
- bus-range: Range of bus numbers associated with this controller
- #address-cells: Address representation for root ports (must be 3)
  - cell 0 specifies the bus and device numbers of the root port:
    [23:16]: bus number
    [15:11]: device number
  - cell 1 denotes the upper 32 address bits and should be 0
  - cell 2 contains the lower 32 address bits and is used to translate to the
    CPU address space
- #size-cells: Size representation for root ports (must be 2)
- ranges: Describes the translation of addresses for root ports and standard
  PCI regions. The entries must be 6 cells each, where the first three cells
  correspond to the address as described for the #address-cells property
  above, the fourth cell is the physical CPU address to translate to and the
  fifth and six cells are as described for the #size-cells property above.
  - The first two entries are expected to translate the addresses for the root
    port registers, which are referenced by the assigned-addresses property of
    the root port nodes (see below).
  - The remaining entries setup the mapping for the standard I/O, memory and
    prefetchable PCI regions. The first cell determines the type of region
    that is setup:
    - 0x81000000: I/O memory region
    - 0x82000000: non-prefetchable memory region
    - 0xc2000000: prefetchable memory region
  Please refer to the standard PCI bus binding document for a more detailed
  explanation.
- #interrupt-cells: Size representation for interrupts (must be 1)
- interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties
  Please refer to the standard PCI bus binding document for a more detailed
  explanation.
- clocks: Must contain an entry for each entry in clock-names.
  See ../clocks/clock-bindings.txt for details.
- clock-names: Must include the following entries:
  - pex
  - afi
  - pll_e
  - cml (not required for Tegra20)
- resets: Must contain an entry for each entry in reset-names.
  See ../reset/reset.txt for details.
- reset-names: Must include the following entries:
  - pex
  - afi
  - pcie_x

Optional properties:
- pinctrl-names: A list of pinctrl state names. Must contain the following
  entries:

Annotation

Implementation Notes