Documentation/devicetree/bindings/pci/nvidia,tegra264-pcie.yaml

Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/pci/nvidia,tegra264-pcie.yaml

File Facts

System
Linux kernel
Corpus path
Documentation/devicetree/bindings/pci/nvidia,tegra264-pcie.yaml
Extension
.yaml
Size
4502 bytes
Lines
150
Domain
Support Tooling And Documentation
Bucket
Documentation
Inferred role
Support Tooling And Documentation: configuration, schema, or hardware description
Status
atlas-only

Why This File Exists

Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

Dependency Surface

Detected Declarations

Annotated Snippet

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pci/nvidia,tegra264-pcie.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NVIDIA Tegra264 PCIe controller

maintainers:
  - Thierry Reding <thierry.reding@gmail.com>
  - Jon Hunter <jonathanh@nvidia.com>

properties:
  compatible:
    const: nvidia,tegra264-pcie

  reg:
    description: |
      Of the six PCIe controllers found on Tegra264, one (C0) is used for the
      internal GPU and the other five (C1-C5) are routed to connectors such as
      PCI or M.2 slots. Therefore the UPHY registers (XPL) exist only for C1
      through C5, but not for C0.
    minItems: 4
    items:
      - description: ECAM-compatible configuration space
      - description: application layer registers
      - description: transaction layer registers
      - description: privileged transaction layer registers
      - description: data link/physical layer registers (not available on C0)

  reg-names:
    minItems: 4
    items:
      - const: ecam
      - const: xal
      - const: xtl
      - const: xtl-pri
      - const: xpl

  interrupts:
    minItems: 1
    maxItems: 4

  dma-coherent: true

  nvidia,bpmp:
    $ref: /schemas/types.yaml#/definitions/phandle-array
    description: |
      Must contain a pair of phandle (to the BPMP controller node) and
      controller ID. The following are the controller IDs for each controller:

      0: C0
      1: C1
      2: C2
      3: C3
      4: C4
      5: C5
    items:
      - items:
          - description: phandle to the BPMP controller node
          - description: PCIe controller ID
            maximum: 5

required:
  - interrupt-map
  - interrupt-map-mask
  - iommu-map
  - msi-map
  - nvidia,bpmp

Annotation

Implementation Notes