Documentation/devicetree/bindings/pci/qcom,pcie-sa8255p.yaml
Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/pci/qcom,pcie-sa8255p.yaml
File Facts
- System
- Linux kernel
- Corpus path
Documentation/devicetree/bindings/pci/qcom,pcie-sa8255p.yaml- Extension
.yaml- Size
- 3740 bytes
- Lines
- 123
- Domain
- Support Tooling And Documentation
- Bucket
- Documentation
- Inferred role
- Support Tooling And Documentation: configuration, schema, or hardware description
- Status
- atlas-only
Why This File Exists
Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.
- Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.
Dependency Surface
dt-bindings/interrupt-controller/arm-gic.h
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pci/qcom,pcie-sa8255p.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm SA8255p based firmware managed and ECAM compliant PCIe Root Complex
maintainers:
- Bjorn Andersson <andersson@kernel.org>
- Manivannan Sadhasivam <mani@kernel.org>
description:
Qualcomm SA8255p SoC PCIe root complex controller is based on the Synopsys
DesignWare PCIe IP which is managed by firmware, and configured in ECAM mode.
properties:
compatible:
const: qcom,pcie-sa8255p
reg:
description:
The base address and size of the ECAM area for accessing PCI
Configuration Space, as accessed from the parent bus. The base
address corresponds to the first bus in the "bus-range" property. If
no "bus-range" is specified, this will be bus 0 (the default).
maxItems: 1
ranges:
description:
As described in IEEE Std 1275-1994, but must provide at least a
definition of non-prefetchable memory. One or both of prefetchable Memory
may also be provided.
minItems: 1
maxItems: 2
interrupts:
minItems: 8
maxItems: 8
interrupt-names:
items:
- const: msi0
- const: msi1
- const: msi2
- const: msi3
- const: msi4
- const: msi5
- const: msi6
- const: msi7
power-domains:
maxItems: 1
dma-coherent: true
iommu-map: true
required:
- compatible
- reg
- ranges
- power-domains
- interrupts
- interrupt-names
allOf:
- $ref: /schemas/pci/pci-host-bridge.yaml#
unevaluatedProperties: false
Annotation
- Immediate include surface: `dt-bindings/interrupt-controller/arm-gic.h`.
- Atlas domain: Support Tooling And Documentation / Documentation.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.