Documentation/devicetree/bindings/pci/qcom,pcie-x1e80100.yaml

Source file repositories/reference/linux-study-clean/Documentation/devicetree/bindings/pci/qcom,pcie-x1e80100.yaml

File Facts

System: Linux kernel
Corpus path: Documentation/devicetree/bindings/pci/qcom,pcie-x1e80100.yaml
Extension: .yaml
Size: 5555 bytes
Lines: 179
Domain: Support Tooling And Documentation
Bucket: Documentation
Inferred role: Support Tooling And Documentation: configuration, schema, or hardware description
Status: atlas-only

Why This File Exists

Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

Dependency Surface

dt-bindings/clock/qcom,x1e80100-gcc.h
dt-bindings/gpio/gpio.h
dt-bindings/interconnect/qcom,x1e80100-rpmh.h
dt-bindings/interrupt-controller/arm-gic.h

Detected Declarations

No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pci/qcom,pcie-x1e80100.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm X1E80100 PCI Express Root Complex

maintainers:
  - Bjorn Andersson <andersson@kernel.org>
  - Manivannan Sadhasivam <mani@kernel.org>

description:
  Qualcomm X1E80100 SoC (and compatible) PCIe root complex controller is based on
  the Synopsys DesignWare PCIe IP.

properties:
  compatible:
    oneOf:
      - const: qcom,pcie-x1e80100
      - items:
          - enum:
              - qcom,glymur-pcie
          - const: qcom,pcie-x1e80100

  reg:
    minItems: 6
    maxItems: 6

  reg-names:
    items:
      - const: parf # Qualcomm specific registers
      - const: dbi # DesignWare PCIe registers
      - const: elbi # External local bus interface registers
      - const: atu # ATU address space
      - const: config # PCIe configuration space
      - const: mhi # MHI registers

  clocks:
    minItems: 6
    maxItems: 7

  clock-names:
    minItems: 6
    items:
      - const: aux # Auxiliary clock
      - const: cfg # Configuration clock
      - const: bus_master # Master AXI clock
      - const: bus_slave # Slave AXI clock
      - const: slave_q2a # Slave Q2A clock
      - const: noc_aggr # Aggre NoC PCIe AXI clock
      - const: cnoc_sf_axi # Config NoC PCIe1 AXI clock

  interrupts:
    minItems: 8
    maxItems: 9

  interrupt-names:
    minItems: 8
    items:
      - const: msi0
      - const: msi1
      - const: msi2
      - const: msi3
      - const: msi4
      - const: msi5
      - const: msi6
      - const: msi7
      - const: global

Annotation

Immediate include surface: `dt-bindings/clock/qcom,x1e80100-gcc.h`, `dt-bindings/gpio/gpio.h`, `dt-bindings/interconnect/qcom,x1e80100-rpmh.h`, `dt-bindings/interrupt-controller/arm-gic.h`.
Atlas domain: Support Tooling And Documentation / Documentation.
Implementation status: atlas-only.

Implementation Notes

This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.