Documentation/devicetree/bindings/pci/renesas,r9a08g045-pcie.yaml

File Facts

System

Linux kernel

Corpus path

Documentation/devicetree/bindings/pci/renesas,r9a08g045-pcie.yaml

Extension

.yaml

Size

8909 bytes

Lines

311

Domain

Support Tooling And Documentation

Bucket

Documentation

Inferred role

Support Tooling And Documentation: configuration, schema, or hardware description

Status

atlas-only

Why This File Exists

Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.

• Repository support layer: documentation, build tooling, samples, user-space helper tools, generated initramfs support, licenses, and validation utilities.
• Touches IRQ or DMA behavior; this matters for the representative real-device path.

Dependency Surface

• dt-bindings/clock/r9a08g045-cpg.h
• dt-bindings/interrupt-controller/arm-gic.h

Detected Declarations

• No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pci/renesas,r9a08g045-pcie.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Renesas RZ/G3S PCIe host controller

maintainers:
  - Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>

description:
  Renesas RZ/G3{E,S} PCIe host controllers comply with PCIe
  Base Specification 4.0 and support up to 5 GT/s (Gen2) for RZ/G3S and
  up to 8 GT/s (Gen3) for RZ/G3E.

properties:
  compatible:
    enum:
      - renesas,r9a08g045-pcie # RZ/G3S
      - renesas,r9a09g047-pcie # RZ/G3E

  reg:
    maxItems: 1

  interrupts:
    minItems: 16
    items:
      - description: System error interrupt
      - description: System error on correctable error interrupt
      - description: System error on non-fatal error interrupt
      - description: System error on fatal error interrupt
      - description: AXI error interrupt
      - description: INTA interrupt
      - description: INTB interrupt
      - description: INTC interrupt
      - description: INTD interrupt
      - description: MSI interrupt
      - description: Link bandwidth interrupt
      - description: PME interrupt
      - description: DMA interrupt
      - description: PCIe event interrupt
      - description: Message interrupt
      - description: All interrupts
      - description: Link equalization request interrupt
      - description: Turn off event interrupt
      - description: PMU power off interrupt
      - description: D3 event function 0 interrupt
      - description: D3 event function 1 interrupt
      - description: Configuration PMCSR write clear function 0 interrupt
      - description: Configuration PMCSR write clear function 1 interrupt

  interrupt-names:
    minItems: 16
    items:
      - const: serr
      - const: serr_cor
      - const: serr_nonfatal
      - const: serr_fatal
      - const: axi_err
      - const: inta
      - const: intb
      - const: intc
      - const: intd
      - const: msi
      - const: link_bandwidth
      - const: pm_pme
      - const: dma
      - const: pcie_evt
      - const: msg

Annotation

• Immediate include surface: `dt-bindings/clock/r9a08g045-cpg.h`, `dt-bindings/interrupt-controller/arm-gic.h`.
• Atlas domain: Support Tooling And Documentation / Documentation.
• Implementation status: atlas-only.
• IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.